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Número de pieza | UPD16661AN-051 | |
Descripción | 160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM | |
Fabricantes | NEC | |
Logotipo | ||
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MOS INTEGRATED CIRCUIT
µPD16661A
160-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM
The µPD16661A is a column (segment) driver containing a RAM capable of full-dot LCD drive. With 160 outputs,
this driver has an on-chip display RAM of 160 × 240 × 2 bits. The driver can be combined with the µPD16666A to
display from 1/8 VGA to VGA (640 × 480 dots).
The µPD16661A is upwardly compatible with the µPD16661.
FEATURES
• Display RAM incorporated : 160 × 240 × 2 bits
• Logic voltage : 3.0 to 3.6 V
• Duty : 1/240
• Output count : 160 outputs
• Capable of gray scale display : 4 gray scales (frame thinning-out)
• Memory management : packed pixel system
• 8/16-bit data bus
ORDERING INFORMATION
Part Number
Package
µPD16661AN-×××
TCP (TAB)
5
µPD16661AN-051
Standard TCP (OLB : 0.2 mm-pitch, pliable-output leads)
Remark The TCP package is custom made, so contact an NEC sales representative with your requirements.
The information in this document is subject to change without notice.
Document No. S11498EJ3V0DS00 (3rd edition)
Date Published November 1998 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
© NEC Corporation 1996,1998
1 page µPD16661A
(10) Data latch (1)
This data latch reads and latches 160-pixel data from the RAM.
(11) Data latch (2)
This data latch synchronizes with the STB signal and latches 160-pixel data.
(12) Level shifter
The level shifter converts the voltage from the operating voltage of the internal circuit (3.3 V) to the voltage of the
liquid-crystal drive circuit and row driver interface (5.0 V).
(13) DEC
The DEC decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V0, V1,
and V2.
(14) Liquid-crystal drive circuit
This circuit selects one of the display OFF signal (/DOFF)-compatible liquid-crystal drive power supplies V0, V1,
or V2, and generates the liquid-crystal applied voltage.
(15) Self-diagnosis circuit
This circuit automatically detects any occurrence of an operation timing lag between the master chip and the
slave chip that has been caused by outside noise, and sends a refresh signal to all the column drivers.
2. MEMORY MAP
A16
00
0F
1D
1F
Address
A0
Description
0 0 0 H Display data of Nos. 0, 2, 4, and 6
:
:
0 0 0 H Display data of Nos. 1, 3, 5, and 7
:
:
FA0 H
Unused
:
FFFH
5
5 Page µPD16661A
6. LSI PLACEMENT AND ADDRESS MANAGEMENT
Addresses can be managed to allow the use of a maximum of eight µPD16661A devices for configuring a liquid-
crystal display of up to VGA size (480 × 640 dots).
Up to eight of these LSIs can be connected to the same data bus and to the /CS, /WE, and /OE pins, which are
shared.
One screen of the liquid-crystal display can be treated as one memory area in the system, so it is not necessary
to decode more than one µPD16661A device.
The PL0, PL1, and PL2 pins are used to specify the LSI No. and determine the LSI placement. The DIR pin is
used to determine the direction (perpendicular, lateral) of the liquid-crystal display.
PL2 PL1 PL0
000
001
010
011
100
101
110
111
LSI No.
No. 0
No. 1
No. 2
No. 3
No. 4
No. 5
No. 6
No. 7
11
11 Page |
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Número de pieza | Descripción | Fabricantes |
UPD16661AN-051 | 160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM | NEC |
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