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PDF UPD16640CN Data sheet ( Hoja de datos )
| Número de pieza | UPD16640CN | |
| Descripción | 300/309-OUTPUT TFT-LCD SOURCE DRIVER 64 GRAY SCALE | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16640C
300/309-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DESCRIPTION
The µ PD16640C is a source driver for TFT-LCD 64-gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits x 3 dots, and 260,000 colors
can be displayed in 64-value outputs γ-corrected by the internal D/A converter and 11 external power supplies.
The clock frequency is 55 MHz MIN. By switching over the number of outputs between 300 and 309, the
µ PD16640C can be used in TFT-LCD panels conforming to the SVGA/XGA standards.
FEATURES
• CMOS level input
• Number of outputs selectable (Osel = H : 300 outputs, Osel = L : 309 outputs)
• 6 bits (gray scale data) x 3 dots input
• 64-value output by 11 external power supplies and internal D/A converter
• Output dynamic range : VSS2 + 0.1 V to VDD2 − 0.1 V
• High-speed data transfer: fMAX.=55 MHz MIN.(internal data transfer speed when VDD1 = 3.0 V)
• Precharge-less output buffer
• Level of γ-corrected power supply can be inverted.
• Input data inversion function (INV)
• Logic power supply (VDD1) : 3.3 V ± 0.3 V
• Driver power supply (VDD2) : 3.3 V ± 0.3 V (Vsel = H)
5.0 V ± 0.5 V (Vsel = L)
ORDERING INFORMATION
Part Number
µ PD16640CN-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC
salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S11269EJ1V1DS00 (1st edition)
Date Published June 1999 NS CP (K)
Printed in Japan
©
1999
1 page  
µ PD16640C
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 11 major points on the γ-characteristic curve of the LCD panel are arbitrarily set by external power supplies V0
through V10. If the display data is 00H or 3FH, gray scale voltage V0 or V10 is output. If the display data is in the
range 01H to 3EH, the high-order 3 bits select an external powers pair Vn+1, Vn. The low-order 3 bits evenly divide
the range of Vn+1, Vn into eight segments by means of D/A conversion (however, the ranges from V9 to V8 and from V2
to V1 are divided into seven segments) to output a 64-grayscale voltage.
DX5 (MSB)
DX4
DX3 DX2 DX1 DX0 (LSB)
High-order 3 bits : γ-corrected power selected
(Vn+1-Vn)
Low-order 3 bits : 3-bit D/A
(range Vn-Vn+1 is divided into 7 or 8 segments)
DX5
DX4
DX3
000
001
010
011
100
101
110
111
Vn+1-Vn
V1-V2
V2-V3
V3-V4
V4-V5
V5-V6
V6-V7
V7-V8
V8-V9
Vn 1
2
3
4
5
6
7
8
Vn+1
000 001 010 011 100 101 110 111
DX2-DX0
0.1 V
VDD2
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
Figure 4-1. Relation between Input Data and γ -corrected Voltage
gray scale supply specified
by 00H
7 segments
8 segments
8 segments
8 segments
8 segments
8 segments
8 segments
7 segments
V10 gray scale supply specified
0.1 V
VSS2
0 7 F 17 1F 27 2F 37 3F
by 3FH
Input data (HEX)
Data Sheet S11269EJ1V1DS00
5
5 Page 
µ PD16640C
Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V,
VSS1 = VSS2 = 0 V)
Parameter
Start pulse delay time
Driver output delay time
Driver output delay time
Input capacitance
Symbol
Condition
tPLH1
CL = 15 pF
tPHL1
tPLH21
tPLH31
tPHL21
tPHL31
VDD2=3.3 V
2 kΩ +75 pF x 2
VO:0.1 V
→3.2 V
VO:3.2 V
→0.1 V
tPLH22
tPLH32
tPHL22
tPHL32
CI1
CI2
VDD2=5.0 V
VO:0.1 V
2 kΩ +75 pF x 2
→4.9 V
VO:4.9 V
→0.1 V
STHR(STHL), TA=25 °C
V0-V10, TA = 25 °C
CI3 STHR(STHL), other than V0-V10,
TA=25 °C
MIN.
TYP.
7
7
2.6
3.0
2.4
3.2
2.2
2.9
2.6
3.6
10
60
10
MAX.
12
12
10
10
10
10
20
100
15
Unit
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
pF
pF
pF
Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = 0 V, tr = tf = 3.0 ns)
Parameter
Symbol
Condition
Clock pulse width
PWCLK
Clock pulse high period
PWCLK (H)
Clock pulse low period
PWCLK (L)
Data setup time
tSETUP1
Data hold time
tHOLD1
Start pulse setup time
tSETUP2
Start pulse hold time
tHOLD2
INV setup time
tSETUP4
INV hold time
tHOLD4
Start pulse low period
tSPL
Start pulse rise time
tSPR1
Osel=H
tSPR2
Osel=L
Final data timing
tSETUP3
CLK-STB time
tINV
STB-CLK time
tLDT
Time between STB and start pulse tCLK-STB
STB-POL time
tSTB-CLK
CLK↑→STB↑
STB↑ →CLK↑
MIN.
18
4
4
4
0
4
0
4
0
2
1
7
7
TYP.
100
103
1
MAX.
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
CLK
CLK
ns
ns
Data Sheet S11269EJ1V1DS00
11
11 Page | ||
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