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PDF UPD16602 Data sheet ( Hoja de datos )
| Número de pieza | UPD16602 | |
| Descripción | 312-OUTPUT TFT-LCD FULL COLOR DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATEwwDw.DataCSheIeRt4UC.comUIT
µPD16602
312-OUTPUT TFT-LCD FULL COLOR DRIVER
The µPD16602 is a TFT-LCD source driver with full color display capability. It is ideal for 1024 × 768 pixel (XGA) class
high definition displays. The internal circuit consists of 12 channels (4 × 3) of analog input pins, 12 channels of 16-bit shift
registers and 312 channels of sample & hold circuits (2 latch type).
Analog display signals are sampled in 12 channels simultaneously by the sample & hold circuits and they are output in
the next line. The output voltage of the sample & hold circuits is as great as 10.5 VP-P and maintains high accuracy with an
output deviation of ±20 mVMAX. Inputting analog display signals that been γ -processed in the previous stage signal
processing circuit allows realization of a high definition 256-gray-scale-equivalent full color display without requiring line
inversion.
FEATURES
• 4 × 3 (RGB)-channel analog input allows display signal input wiring to be reduced.
• High dynamic range (10.0 VP-PMIN. VDD2 = 11.0 V)
• High accuracy sample & hold circuits (output deviation; ±20 mVMAX., ±5.0 mVTYP.)
• High-speed sampling frequency (for both analog and digital; fmax. = 20 MHzMIN.)
• Low power control (reduction of output buffer bias current) function on chip
(operating power consumption; 82 mWTYP., VDD2 = 12.5 V)
• Bi-directional data store function on chip
• Corresponding to high-density mounting (slim TCP)
ORDERING INFORMATION
Part Number
µPD16602N- × × ×
TCP
Package
Document No. S10671EJ1V0DS00 (1st edition)
Date Published August 1998 N CP(K)
Printed in Japan
© 1998
1 page  
3. PIN DESCRIPTION
µPD16602
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Pin Symbol
S1 to S312
CLK
DR0 to DR3
DG0 to DG3
DB0 to DB3
R/L
SPR
SPL
Note
PL/NL
S/D
Note
HS
LPC
BIAS1
BIAS2
VDD1
VDD2(D)
VDD2(A)
VCOM
VSS1
VSS2(D)
VSS2(A)
VSS2(C)
TEST
Pin Name
Driver outputs
Clock input
Analog display
signal inputs
Description
Output pins for sampled analog image signals. When driven with VDD2 = 12.5 V, a
11.5 VP-P analog voltage whose input/output characteristic is gain 1 is output.
This pin reads the start pulse at the rising of CLK and starts sampling of analog
display signals in 12 channels simultaneously. The active edges of CLK are all
rising edges.
Analog image signal input pins. Please input analog display signals by inverting the
polarity for each display line.
Shift direction
switching input
Start pulse input/
output
Start pulse input/
output
Polarity inversion
input
Arrangement
switching input
Horizontal
synchronous input
Low power control
input
Bias voltage inputs
Logic power supply
Driver power supply
Driver power supply
Common power
supply
Logic ground
Driver ground
Driver ground
Driver ground
Test pin
The shift direction of the shift register is as follows.
R/L = H (right shift) ; SPR input, S1 → S312, SPL output
R/L = L (left shift) ; SPL input, S312 → S1, SPR output
R/L = H (right shift) ; start pulse input pin
R/L = L (left shift) ; start pulse output pin
R/L = H (right shift) ; start pulse output pin
R/L = L (left shift) ; start pulse input pin
S/D = L; When PL/NL = H, Both odd number pin and even number pin samples
negative analog display signals and outputs positive analog signals from the
driver output.
When PL/NL = L, Both odd number pin and even number pin samples
positive analog display signals and outputs negative analog signals from the
driver output.
S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals
and outputs positive analog signals from the driver output. Even number pin
samples positive analog display signals and outputs negative analog signals
from the driver output.
When PL/NL = L, Odd number pin samples positive analog display signals
and outputs negative analog signals from the driver output. Even number pin
samples negative analog display signals and outputs positive analog signals
from the driver output.
S/D = H; Complying with one side arrangement dot inverting.
S/D = L; Complying with both sides arrangement dot inverting.
This pin shuts off the output at the falling edge and then outputs analog display
signals at the rising. When HS = L, after the driver output pin goes to high impedance
this pin switches PL/NL and resets the internal hold capacity and output buffer to the
VCOM level.
This pin shuts off the output buffer low current supply and increases the output
impedance. The LPC = “H” mode allows the static current consumption to be
reduced by approximately 20 %.
These pins control the current consumption of the output buffer by applying a
stabilized external power supply.
3.3 V ±0.3 V
13.5 VMAX.
13.5 VMAX.
This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage
follower, etc.
Logic ground
High voltage block (level shifter)
High voltage block (output buffer)
High voltage block (sample & hold)
“L” or left open
Note Sample & hold operation and reset operation of the output buffer capacitance and VCOM level are performed
by the PL/NL and HS logic.
5
5 Page 
6. ELECTRIC SPECIFICATION
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS(D), (A), (C) = 0 V)
Item
Logic supply voltage
Logic input voltage
Logic output voltage
Driver supply voltage
Display signal input voltage
Driver output voltage
Driver output current
Operating temperature range
Storage temperature range
Symbol
VDD1
VIN
VO1
VDD2 (D), (A)
VIN (A)
VO2
IO2
TA
Tstg
Rating
–0.5 to +6.5
–0.5 to VDD1 +0.5
–0.5 to VDD1 +0.5
–0.5 to +15
–0.5 to VDD2 +0.5
–0.5 to VDD2 +0.5
±10
–10 to +75
–40 to +125
µPD16602
www.DataSheet4U.com
Unit
V
V
V
V
V
V
mA
°C
°C
RECOMMENDED OPERATING RANGE (TA = –10 to 75°C, VSS = 0 V)
Item
Logic supply voltage
High-level input voltage
Low-level input voltage
Driver supply voltage
Display signal input
Driver output voltage
Bias current
Bias voltage
Symbol
VDD1
VIH
VIL
VDD2
VIN (A)
VO
IBIAS1, 2
VBIAS1
VBIAS2
MIN.
3.0
0.7 VDD1
11.0
VSS +0.5
VSS +0.5
100
VSS +4.5
VDD2 –7.5
TYP.
3.3
12.5
VSS +5.0
VDD2 –7.0
MAX.
3.6
0.3 VDD1
13.5
VDD2 –0.5
VDD2 –0.5
VSS +5.5
VDD2 –6.5
Unit
V
V
V
V
V
V
µA
V
V
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16602.PDF ] | |
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