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PDF UPD16341 Data sheet ( Hoja de datos )
| Número de pieza | UPD16341 | |
| Descripción | 96-BIT AC-PDP DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16341
96-BIT AC-PDP DRIVER
• DESCRIPTION
The µ PD16341 is high withstand voltage CMOS driver designed for flat display panels such as PDPs, VFDs and
ELs. It consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage CMOS driver. The logic
block is designed to operate using a 5-V power supply interface enabling direct connection to a gate array or a
microcontroller. In addition, the µ PD16341 achieves low power dissipation by employing the CMOS structure while
having a high withstand voltage output (120 V, +15/−25 mA MAX.).
FEATURES
• 2-/3-/4-/6-ch input port switching is possible using IBS1 and IBS2 pins
• Data control with transfer clock (external) and latch
• High-speed data transfer (fMAX. = 40 MHz MIN. at data latch)
(fMAX. = 25 MHz MIN. at cascade connection)
• • High withstand output voltage: 120 V, +15/–25 mA MAX.
• 5-V CMOS input interface
• High withstand voltage CMOS structure
• ORDERING INFORMATION
Part Number
µ PD16341
Package
Module
Remark Consult an NEC sales representative regarding the module. Since the module characteristics is
based on the module specifications, there may be differences between the contents written in this
document and real characteristics.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14076EJ2V0DS00 (2nd edition)
Date Published March 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1999, 2000
1 page  
µ PD16341
1. BLOCK DIAGRAM (4) (IBS1 = L, IBS2 = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER)
HZ
/LBLK
/HBLK
/LE
VDD2
A1
CLK
R,/L
B1
/CLR
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
SR1Note
A1
CLK
S1
S7
RB1,/LCLRS91
SR2Note
A2
CLK
S2
S8
RB2,/LCLRS92
SR3Note
A3
CLK
S3
S9
RB3,/LCLRS93
SR4Note
A4 S4
CLK S10
RB4,/LCLRS94
SR5Note
A5 S5
CLK S11
RB5,/LCLRS95
SR6Note
A6 S6
CLK S12
RB6,/LCLRS96
LE
S1
S2 /L1
S3
S4
S5
S6
S91
S92
S93
S94
S95
S96 /L96
O1
VSS2
VDD2
O96
Note SRn: 16-bit shift register
VSS2
Data Sheet S14076EJ2V0DS00
5
5 Page 
4. TIMING CHART (4) (IBS1 = L, IBS2 = L: 6-BIT INPUT, RIGHT SHIFT)
/CLR
CLK
A1(B6)
A2(B5)
A3(B4)
A4(B3)
A5(B2)
A6(B1)
S1(S96)
S2(S95)
S3(S94)
S4(S93)
S5(S92)
S6(S91)
S7(S90)
/LE
/HBLK
/LBLK
HZ
Latch at falling edge
O1(O96)
O2(O95)
O3(O94)
O4(O93)
O5(O92)
O6(O91)
O7(O90)
Remark Values in parentheses are when R,/L = L.
µ PD16341
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
Data Sheet S14076EJ2V0DS00
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UPD16341.PDF ] | |
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