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PDF UPA1523 Data sheet ( Hoja de datos )
| Número de pieza | UPA1523 | |
| Descripción | P-CHANNEL POWER MOS FET ARRAY SWITCHING INDUSTRIAL USE | |
| Fabricantes | NEC | |
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DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
µPA1523B
P-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DESCRIPTION
The µPA1523B is P-channel Power MOS FET Array that built
in 4 circuits designed for solenoid, motor and lamp driver.
FEATURES
• Full Mold Package with 4 Circuits
• –4 V driving is possible
• Low On-state Resistance
RDS(on)1 = 0.8 Ω MAX. (@VGS = –10 V, ID = –1 A)
RDS(on)2 = 1.3 Ω MAX. (@VGS = –4 V, ID = –1 A)
• Low Input Capacitance Ciss = 190 pF TYP.
ORDERING INFORMATION
Type Number
µPA1523BH
Package
10 Pin SIP
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Drain to Source Voltage (VGS = 0) VDSS
–60 V
Gate to Source Voltage (VDS = 0) VGSS(AC) 20 V
Drain Current (DC)
ID(DC)
2.0 A/unit
Drain Current (pulse)
ID(pulse) *1 8.0 A/unit
Total Power Dissipation
PT1 *2 28 W
Total Power Dissipation
PT2 *3 3.5 W
Channel Temperature
TCH 150 ˚C
Storage Temperature
Tstg –55 to + 150 ˚C
Single Avalanche Current
IAS *4
–2.0
A
Single Avalanche Energy
EAS *4 0.4 mJ
PACKAGE DIMENSIONS
in millimeters
26.8 MAX.
4.0
1.4 0.6 ± 0.1
2.54
1.4
0.5 ± 0.1
1 2 3 4 5 6 7 8 910
CONNECTION DIAGRAM
35 79
24 68
1 10
ELECTRODE CONNECTION
2, 4, 6, 8 : Gate
3, 5, 7, 9 : Drain
1, 10 : Source
*1 PW ≤ 10 µs, Duty Cycle ≤ 1%
*3 4 Circuits, TA = 25 ˚C
*2 4 Circuits, TC = 25 ˚C
*4 Starting TCH = 25 ˚C, VDD = –30 V, VGS = –20 V → 0, RG = 25 Ω,
L = 100 µH
Build-in Gate Diodes are for protection from static electricity in handing.
In case high voltage over VGSS is applied, please append gate protection circuits.
Document No. G11331EJ1V0DS00
Date Published May 1996 P
Printed in Japan
The information in this document is subject to change without notice.
©
1996
1 page  
µPA1523B
1 000
100
10
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
Rth(CH-A) 4ircuits
3ircuits
2ircuits
1ircuit
Rth(CH-C)
1.0
0.1
100 µ 1 m
10 m
100 m
1
PW - Pulse Width - s
10
Single Pulse
100 1 000
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
VDS = –10 V
Pulsed
10
TA = –25 ˚C
25 ˚C
75 ˚C
1.0 125 ˚C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
1.5 Pulsed
ID = –2 A
1.0
–1 A
–0.4 A
0.5
0.1
–0.01
–0.1 –1.0
ID - Drain Current - A
–10
1 500
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
Pulsed
1 000
500
0
VGS = –4 V
VGS = –10 V
–0.1 –1.0
ID - Drain Current - A
–10
0 –10 –20
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUTOFF VOLTAGE vs.
CHANNEL TEMPERATURE
VDS = –10 V
–2 ID = –1 mA
–1
0
–50
0 50 100 150
TCH - Channel Temperature - ˚C
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPA1523.PDF ] | |
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