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PDF UMA1015AM Data sheet ( Hoja de datos )
| Número de pieza | UMA1015AM | |
| Descripción | Low-power dual frequency synthesizer for radio communications | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
UMA1015AM
Low-power dual frequency
synthesizer for radio
communications
Product specification
Supersedes data of 1997 Jun 10
File under Integrated Circuits, IC17
1997 Sep 03
1 page  
Philips Semiconductors
Low-power dual frequency synthesizer
for radio communications
Product specification
UMA1015AM
Table 1 Synthesizer ratio of reference divider
SR SYNTHESIZER A SYNTHESIZER B
0R
R
1R
2R
Phase comparators
For each synthesizer, the outputs of the main and
reference dividers drive a phase comparator where a
charge pump produces phase error current pulses for
integration in an external loop filter. The charge pump
current is set by an external resistance RSET at pin ISET,
where a temperature-independent voltage of 1.1 V is
generated. RSET should be between 12 and 60 kΩ.
The charge pump current, ICP, can be programmed to be
either (12 × ISET) or (24 × ISET) with a maximum of 2.3 mA.
The dead zone, caused by finite switching of current
pulses, is cancelled by an internal delay in the phase
detector thus giving improved linearity. The charge pump
has a separate supply, VCC, which helps to reduce the
interference on the charge pump output from other parts of
the circuit. VCC can be higher than VDD1 if a wider range on
the VCO input is required. VCC must not be less than VDD1.
Voltage doubler
If required, there is a voltage doubler on-chip to supply the
charge pumps at a higher level than the nominal available
supply. The doubler operates from the digital supply VDD1,
and is internally limited to a maximum output of 6 V.
An external capacitor is required on pin VCC for smoothing,
the capacitor required to develop the extra voltage is
integrated on-chip. To minimize the noise being introduced
to the charge pump output from the voltage doubler, the
doubler clock is suppressed (provided both loops are
in-lock) for the short time that the charge pumps are active.
The doubler clock (RF/64) is derived from whichever main
divider is operating (synthesizer A has priority). While both
synthesizers are powered down (and the doubler is
enabled), the doubler clock is supplied by a low-current
internal oscillator. The doubler can be disabled by
programming the bit VDON to logic 0, in order to allow an
external charge pump supply to be used.
Out-of-lock indication/output ports
There is a common lock detector on-chip for the
synthesizers. The lock condition of each, or both loops, is
output via an open-drain transistor which drives
pin P0/OOL (when out-of-lock, the transistor is turned on
and therefore the output is forced LOW). The lock
condition output is software selectable (see Table 4).
An out-of-lock condition is flagged when the phase error is
greater than TOOL, which is approximately 30 ns.
The out-of-lock flag is only released after the first reference
cycle where the phase error is less than TOOL.
The out-of-lock function can be disabled, via the serial bus,
and the pin P0/OOL can be used as a port output. Three
other port outputs P1, P2 and P3 (open-drain transistors)
are also available.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable).
The data sent to the device is loaded in bursts framed
by E. Programming clock edges are ignored until E goes
active LOW. The programmed information is loaded into
the addressed latch when E returns inactive (HIGH). This
is allowed when CLK is in either state without causing any
consequences to the register data. Only the last 21 bits
serially clocked into the device are retained within the
programming register. Additional leading bits are ignored,
and no check is made on the number of clock pulses.
The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during power-down of both
synthesizers.
However when either synthesizer A or synthesizer B or
both are powered-on, the presence of a TCXO signal is
required at pin 8 (fXTALIN) for correct programming.
Data format
Data is entered with the most significant bit first.
The leading bits make up the data field, while the trailing
four bits are an address field. The address bits are
decoded on the rising edge of E. This produces an internal
load pulse to store the data in the addressed latch.
To ensure that data is correctly loaded on first power-up,
E should be held LOW and only taken HIGH after having
programmed an appropriate register. To avoid erroneous
divider ratios, the pulse is inhibited during the period when
data is read by the frequency dividers. This condition is
guaranteed by respecting a minimum E pulse width after
data transfer. The data format and register bit allocations
are shown in Table 2.
1997 Sep 03
5
5 Page 
Philips Semiconductors
Low-power dual frequency synthesizer
for radio communications
TYPICAL PERFORMANCE CHARACTERISTICS
12
handbook, full pagewidth
IDD
(mA)
10
8
(1)
(2)
(3)
6
Product specification
UMA1015AM
MGK784
4
2
2.5
3
3.5
4
4.5
5
VDD (V)
5.5
(1) Tamb = +90 °C.
(2) Tamb = +25 °C.
(3) Tamb = −35 °C.
Fig.4 Typical IDD as a function of VDD with both synthesizers on and voltage doubler disabled.
2.0
handbook, full pagewidth
ICPA 1.6
(mA)
1.2
(1)
MGK783
(2)
0.8
0.4
0
−0.4
−0.8
−1.2
−1.6
−2.0
0
RSET = 15 kΩ;
CRA = 1.
(1)
1
(1) VCC = 2.7 V.
2
(2) VCC = 6.0 V.
3
(2)
4 5 VCPA (V) 6
Fig.5 Typical charge pump current as a function of CPA voltage with Tamb = 25 °C.
1997 Sep 03
11
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| PDF Descargar | [ Datasheet UMA1015AM.PDF ] | |
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