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PDF US3018 Data sheet ( Hoja de datos )
| Número de pieza | US3018 | |
| Descripción | 5 BIT PROGRAMMABLE SYNCHRONOUS BUCK PLUS LDO CONTROLLER AND 200mA LDO ON BOARD | |
| Fabricantes | UNISEM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de US3018 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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US3018
5 BIT PROGRAMMABLE SYNCHRONOUS BUCK PLUS
FEATURES
LDO CONTROLLER AND 200mA LDO ON BOARD
PRELIMINARY DATASHEET
DESCRIPTION
Provides Single Chip Solution for Vcore, GTL+
& Clock Supply
200 mA On board LDO regulator
Designed to meet the latest Intel specification
for Pentium II™
On board DAC programs the output voltage
from 1.3V to 3.5V
Linear regulator controller on board for 1.5V
GTL+ supply
Loss less Short Circuit Protection with HICCUP
Synchronous operation allows maximum effi-
ciency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Soft Start
High current totem pole driver for direct driv-
ing of the external Power MOSFET
Power Good function Monitors all Outputs
OVP Circuitry Protects the Switcher Output and
generates a Fault signal
Thermal Shutdown
Logic Level Enable Input
APPLICATIONS
The US3018 controller IC is specifically designed to meet
Intel specification for Pentium II™ microprocessor ap-
plications as well as the next generation of P6 family
processors. The US3018 provides a single chip con-
troller IC for the Vcore , LDO controller for GTL+
and an internal 200mA regulator for clock supply
which are required for the Pentium II applications.
These devices feature a patented topology that in com-
bination with a few external components as shown in
the typical application circuit ,will provide in excess of
18A of output current for an on- board DC/DC converter
while automatically providing the right output voltage via
the 5 bit internal DAC. The US3018 also features, loss
less current sensing for both switchers by using the
Rds-on of the high side Power MOSFET as the sens-
ing resistor, internal current limiting for the clock
supply, a Power Good window comparator that switches
its open collector output low when any one of the out-
puts is outside of a pre programmed window. Other fea-
tures of the device are ; Undervoltage lockout for both
5V and 12V supplies, an external programmable soft
start function , programming the oscillator frequency via
an external resistor, OVP circuitry for both switcher out-
puts and an internal thermal shutdown.
Total Power Soloution for Pentium II processor
application
TYPICAL APPLICATION
5V
3.3V
Vout3
US3018 SWITCHER1
CONTROL
LINEAR
LINEAR
CONTROL REGULATOR
Vout1
3018app3-1.1
Vout2
Notes: Pentium II is trade mark of Intel Corp.
PACKAGE ORDER INFORMATION
Ta (°C)
0 TO 70
Device
US3018CW
Rev. 1.4
12/8/00
Package
24 pin Plastic SOIC WB
4-1
1 page  
US3018
PIN# PIN SYMBOL Pin Description
19 VSEN1
12 VIN2
20 OCSET1
23 PHASE1
9 SS
10 FAULT/Rt
15 GATE3
16 FB3
13 VOUT2
11 FB2
14 GND
21 PGND
22 LGATE1
24 UGATE1
1 V12
8 V5
17 En
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is the input that provides power for the internal LDO regulator. It is also monitored
for the under voltage and over voltage conditions.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the C.S threshold depending on the Rds of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin provides the soft start for the switching regulator. An internal resistor charges an
external capacitor that is conected from 5V supply to this pin which ramps up the outputs
of the switching regulators, preventing the outputs from overshooting as wellas limiting
the input current. The second function of the Soft Start cap is to provide long off time
(HICCUP) for the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor . When used as a fault detector, if the
switcher output exceed the OVP trip point, the FAULT pin switches to 12V and the soft
start cap is discharged. If the FAULT pin is to be connected to any external circuitry, it
needs to be buffered as shown in the application circuit.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is GATE3.
This pin is the output of the internal LDO regulator.
This pin provides the feedback for the internal LDO regulator that its output is Vout4.
This pin serves as the ground pin and must be conected directly to the ground plane.
This pin serves as the Power ground pin and must be conected directly to the GND plane
close to the source of the synchronous MOSFET. A high frequency capacitor (typically 1
uF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
Output driver for the high side power MOSFET for the Core supply.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1 uF) must be placed close to this pin and
PGND pin and be connected directly from this pin to the GND plane for the noise free
operation.
5V supply voltage. A high frequency capacitor (0.1 to 1 uF) must be placed close to this
pin and connected from this pin to the GND plane for noise free operation.
This pin is a TTL compatible Enable pin. When this pin is left open or pulled high, the
device is enabled and when is pulled low, it will disable the switcher and the LDO
controller (Vout 3) leaving the internal 200mA regulator operational. When signal is
given to enable the device, both switcher and Vout 3 will go through soft start, the
same as during start up.
Rev. 1.4
12/8/00
4-5
5 Page 
US3018
Application Information
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regula-
tor must meet for Vcore :
a) Vo=2.8V , Io=14.2A, ∆Vo=185mV, ∆Io=14.2A
b) Vo=2V , Io=14.2A, ∆Vo=140mV, ∆Io=14.2A
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total ∆Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as :
ESR ≤ 100 = 7 mΩ
14.2
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX
, 1500uF, 6.3V has an ESR of less than 36 mΩ typ .
Selecting 6 of these capacitors in parallel has an ESR
of ≈6 mΩ which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic “FA” series or
the Nichicon “PL” series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number
of output capacitors, by level shifting the DC regu-
lation point when transitioninig from light load to
full load and vice versa. To accomplish this, the out-
put of the regulator is typically set about half the DC
drop that results from light load to full load. For example,
if the total resistance from the output capacitors to the
Slot 1 and back to the GND pin of the 3018 is 5mΩ and
if the total ∆I, the change from light load to full load is
14A, then the output voltage measured at the top of the
resistor divider which is also connected to the output
capacitors in this case, must be set at half of the 70 mV
or 35mV higher than the DAC voltage setting. This in-
tentional voltage level shifting during the load transient
eases the requirement for the output capacitor ESR at
the cost of load regulation. One can show that the new
ESR requirement eases up by half the total trace re-
sistance. For example, if the ESR requirement of the
output capacitors without voltage level shifting must be
7mΩ then after level shifting the new ESR will only need
to be 8.5mΩ if the trace resistance is 5mΩ (7+5/2=9.5).
However, one must be careful that the combined “volt-
age level shifting” and the transient response is still within
the maximum tolerance of the Intel specification. To in-
sure this, the maximum trace resistance must be less
than:
Rs≤ 2(Vspec - 0.02*Vo - ∆Vo)/∆I
Where :
Rs=Total maximum trace resistance allowed
Vspec=Intel total voltage spec
Vo=Output voltage
∆Vo=Output ripple voltage
∆I=load current step
For example, assuming:
Vspec=±140 mV=±0.1V for 2V output
Vo=2V
∆Vo=assume 10mV=0.01V
∆I=14.2A
Then the Rs is calculated to be:
Rs≤ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mΩ
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6 mΩ , the power dissipated is
(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to
be dissipated in a system. So, if the Rs=5mΩ, then the
power dissipated is about 1W which is much more ac-
ceptable. If level shifting is not implemented, then the
maximum output capacitor ESR was shown previously
to be 7mΩ which translated to ≈ 6 of the 1500uF,
6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the
maximum ESR becomes 9.5mΩ which is equivalent to
≈ 4 caps. Another important consideration is that if a
trace is being used to implement the resistor, the
power dissipated by the trace increases the case
temperature of the output capacitors which could
seriously effect the life time of the output capaci-
tors.
Output Inductor Selection
The output inductance must be selected such that un-
der low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage is
drooping during a load current step.
Rev. 1.4
12/8/00
4-11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet US3018.PDF ] | |
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