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PDF UPI-452 Data sheet ( Hoja de datos )
| Número de pieza | UPI-452 | |
| Descripción | CHMOS PROGRAMMABLE I/O PROCESSOR | |
| Fabricantes | Intel Corporation | |
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UPI-452
CHMOS PROGRAMMABLE I O PROCESSOR
83C452 - 8K c 8 Mask Programmable Internal ROM
80C452 - External ROM EPROM
Y 83C452 80C452 3 5 to 14 MHz Clock
Rate
Y Software Compatible with the MCS-51
Family
Y 128-Byte Bi-Directional FIFO Slave
Interface
Y Two DMA Channels
Y 256 c 8-Bit Internal RAM
Y 34 Additional Special Function
Registers
Y 40 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y Boolean Processor
Y Bit Addressable RAM
Y 8 Interrupt Sources
Y Programmable Full Duplex Serial
Channel
Y 64K Program Memory Space
Y 64K Data Memory Space
Y 68-Pin PGA and PLCC
(See Packaging Spec Order 231369)
The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I O Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip The UPI-452
is the newest member of Intel’s UPI family of products It is a general-purpose slave I O Processor that allows
the designer to grow a customized interface solution
The UPI-452 contains a complete 80C51 with twice the on-chip data and program memory The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU To both the
external host and the internal CPU the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data The FIFO manages the transfer of data independent of the UPI-452 core CPU and
generates an interrupt or DMA request to either CPU host or internal as a FIFO service request
The FIFO consists of two channels the Input FIFO and the Output FIFO The division of the FIFO module
array 128 bytes between Input channel and Output channel is programmable by the user Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte
Additionally Immediate Commands allow direct interrupt driven bi-directional communication between the
UPI-452 internal CPU and external host CPU bypassing the FIFO
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another
As many as 64K bytes can be transferred in a single DMA operation Three distinct memory spaces may be
used in DMA operations Internal Data Memory External Data Memory and the Special Function Registers
(including the FIFO IN FIFO OUT and Serial Channel Special Functions Registers)
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
November 1994
Order Number 231428-006
1 page  
UPI-452
LIST OF TABLES AND FIGURES
Figures
1 Architectural Block Diagram
2 UPI 452 68-Pin PLCC Pinout Diagram
3 UPI-452 Conceptual Block Diagram
4 UPI-452 Functional Block Diagram
5 Input FIFO Channel Functional Block Diagram
6 Output FIFO Channel Functional Block Diagram
7a Handshake Mechanisms for Handling Immediate Command IN Flowchart
7b Handshake Mechanisms for Handling Immediate Command OUT Flowchart
8 DMA Transfer from External to External Memory
9 DMA Transfer from External to Internal Memory
10 DMA Transfer from Internal to External Memory
11 DMA Transfer Waveform Internal to Internal Memory
12 Disabling FIFO to Host Slave Interface Timing Diagram
Tables
1 Input FIFO Channel Registers
2 Output FIFO Channel Registers
3 UPI-452 Address Decoding
4 DMA Accessible Special Function Registers
5 DMA Mode Control - PCON SFR
6 Interrupt Priority
7 Interrupt Vector Addresses
8 Slave Bus Interface Status During FIFO DMA Freeze Mode
9 FIFO SFR’s Characteristics During FIFO DMA Freeze Mode
10 Threshold SFRs Range of Values and Number of Bytes to be Transferred
11a Internal Memory Addressing
11b 80C51 Special Function Registers
11c UPI-452 Additional Special Function Registers
12 Program Status Word (PSW)
13 PCON Special Function Register
2
6
10
11
13
15
17
17
31
31
31
32
36
13
15
23
26
29
32
32
35
38
39
41
42
42
44
44
5
5 Page 
UPI-452
Figure 4 UPI-452 Functional Block Diagram
231428 – 8
The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility If the entire 128 byte FIFO is
allocated to the Input channel a high performance
Host can transfer up to 128 bytes at one time then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO Vari-
ous handshake signals allow the external Host to
operate independently and without frequent monitor-
ing of the UPI-452 internal CPU The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses Three slave bus
interface handshake methods are supported by the
UPI-452 DMA Interrupt and Polled
The FIFO is nine bits wide The ninth bit acts as a
command data flag Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs DSCs are written to
the input FIFO by the Host via a unique external
address DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Func-
tion Register (SFR) When encountered by the host
or internal CPU a Data Stream Command can be
used as an address vector to user defined service
routines DSCs provide synchronization of data and
commands between the Host and internal CPU
FIFO PROGRAMMABLE FEATURES
Size of Input Output Channels
The 128 bytes of FIFO space can be allocated be-
tween the Input and Output channels via the Chan-
nel Boundary Pointer (CBP) SFR This register con-
tains the number of address locations assigned to
the Input channel The remaining address locations
are automatically assigned to the Output FIFO The
CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-Ex-
ternal Host Interface FIFO DMA Freeze Mode de-
scription) The CBP is initialized to 40H (64 bytes)
upon reset
The number in the Channel Boundary Pointer SFR is
actually the first address location of the Output
FIFO Writing to the CBP SFR reassigns the Input
and Output FIFO address space Whenever the CBP
is written the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
the CBP SFR
All of the FIFO space may be assigned to one chan-
nel In such a situation the other channel’s data path
consists of a single SFR (FIFO IN COMMAND IN or
FIFO OUT COMMAND OUT SFR) location
CBP
Register
0
1
2
3
4
7B
7C
7D
7E
7F
Input FIFO
Size
1
1
2
3
4
123
124
125
128
128
Output FIFO
Size
128
128
126
125
124
5
4
3
1
1
11
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