UPD98401A Datasheet PDF - NEC
Part Number | UPD98401A | |
Description | ATM SAR CHIP | |
Manufacturers | NEC | |
Logo | ||
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MOS INTEGRATED CIRCUIT
µPD98401A
ATM SAR CHIP
DESCRIPTION
The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells.
This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions
of the AAL-5 SAR sublayer and ATM layer.
The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software.
Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your
system.
µPD98401A User’s Manual: S12054E
FEATURES
• Conforms to ATM Forum
• AAL-5 SAR sublayer and ATM layer functions
• Hardware support of AAL-5 processing
• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function
• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic
• Supports up to 32K virtual channels (VC)
• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to
set different transmission rate for each VC
• Interface and commands for controlling PHY device
• Employs “UTOPIA interface” as cell data interface with PHY device
- Octet-level handshake
- Cell-level handshake
• 32-bit general-purpose bus interface
• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)
• JTAG boundary scan test function (IEEE1149.1)
• CMOS technology
• +5 V single power source
Remark In this document, an active low pin is indicated by ×××_B (_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition)
Date Published February 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997
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µPD98401A
PIN NAMES
ABRT_B
: Abort
AD31_AD0
: Address/Data
ASEL_B
: Slave Address Select
ATTN_B
: Attention/Burst Frame
CA17-CA0
: Control Memory Address
CBE_B3_CBE_B0 : Local Port Byte Enable
CD31-CD0
: Control Memory Data
CLK : Clock
COE_B
: Control Memory Output Enable
CPAR3-CPAR0 : Control Memory Parity
CWE_B
: Control Memory Write Enable
DBMD
: DMA Bus Monitor Data
DBMF
: DMA Bus Monitor First
DBML
: DMA Bus Monitor Last
DBVC
: DMA Bus Monitor VC
DBMR
: DMA Bus Monitor Remaining
DR/W_B
: DMA Read/Write
EMPTY_B/RxCLAV : PHY Output Buffer Empty
ERR_B
: Error
FULL_B/TxCLAV : PHY Buffer Ful
GND
: Ground
GNT_B
: Grant
INITD
: Initialization Disable
INTR_B
: Interrupt
JCK : JTAG Test Pin
JDI : JTAG Test Pin
JDO
: JTAG Test Pin
JMS
: JTAG Test Pin
JRST_B
: JTAG Test Pin
OE_B
: Output Enable
PAR3-PAR0
: Bus Parity
PHCE_B
PHINT_B
PHOE_B
PHRW_B
RCLK
RDY_B
RENBL_B
RSOC
RST_B
Rx7-Rx0
SLE_B
SIZE2-SIZE0
SR/W_B
TCLK
TENBL_B
TSOC
TRF_B
Tx7-Tx0
VDD
: PHY Chip Enable
: PHY Interrupt
: PHY Output Enable
: PHY Read/Write
: Receive Clock
: Target Ready
: Receive Enable
: Receive Start Cell
: Reset
: Receive Data Bus
: Slave Select
: Burst Size
: Slave Read/Write
: Transmit Clock
: Transmit Enable
: Transmit Start of Cell
: Delay Select
: Transmit Data Bus
: Power Supply
Data Sheet S12100EJ3V0DS00
5
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