UPD784927GC Datasheet PDF - NEC
Part Number | UPD784927GC | |
Description | 16-BIT SINGLE-CHIP MICROCONTROLLER | |
Manufacturers | NEC | |
Logo | ||
There is a preview and UPD784927GC download ( pdf file ) link at the bottom of this page. Total 70 Pages |
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MOS INTEGRATED CIRCUIT
µPD784927, 784928, 784927Y, 784928Y
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-
speed, high-performance 16-bit CPU for VCR software servo control.
The µPD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible
with multi-master.
They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer
unit) for software servo control and VCR analog circuits.
Flash memory models, the µPD78F4928 and µPD78F4928Y, are under development.
The functions of the µPD784927 is described in detail in the following User’s Manual. Be sure to read this
manual before designing your system.
µPD784928, 784928Y Subseries User’s Manual - Hardware
: U12648E
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
• High instruction execution speed realized by 16-bit CPU core
• Minimum instruction execution time: 250 ns (with 8 MHz internal clock)
• High internal memory capacity
Item
Part Number µPD784927, 784927Y µPD784928, 784928Y
Internal ROM capacity
96K bytes
128K bytes
Internal RAM capacity
2048 bytes
3584 bytes
• VCR analog circuits conforming to VHS Standard
• CTL amplifier
• DFG amplifier
• Reel FG comparator (2 channels)
• RECCTL driver (rewritable) • DPG amplifier
• CSYNC comparator
• CFG amplifier
• DPFG separation circuit (ternary separation circuit)
• Timer unit (super timer unit) for servo control
• Serial interface : 3 channels
• 3-wire serial I/O : 2 channels
• I2C bus interface: 1 channel
• A/D converter: 12 channels (conversion time: 10 µs)
• Low-frequency oscillation mode: main system clock frequency = internal clock frequency
• Low-power consumption mode: CPU can operate with a subsystem clock.
• Supply voltage range: VDD = +2.7 to 5.5 V
• Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the µPD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12255EJ2V0DS00 (2nd edition)
Date Published December 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997,1999
|
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µPD784927, 784928, 784927Y, 784928Y
PIN CONFIGURATION (Top View)
• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)
µPD784927GC-×××-8EUNote 1, 784928GC-×××-8EUNote 1
µPD784928YGC-×××-8EU, 784928YGC-×××-8EUNote 1
P84/PWM2/SDANote 2
P83/ROTC
P82/HASW
P80
P57
P56
P55
P54
P53
P52
P51
P50
VSS
VDD
P47
P46
P45
P44
P43
P42
P41
P40
P07
P06
P05
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 66
11 65
12 64
13 63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P65/HWIN/DPGMON
P64/BUZ/DFGMON
P103/CSYNCIN
P102/REEL0IN/INTP3
P101/REEL1IN
DFGIN
P100/DPGIN
CFGCPIN
CFGAMP0
CFGIN
AVDD1
AVSS1
VREFC
CTLOUT2
CTLOUT1
CTLIN
RECCTL−
RECCTL+
CTLDLY
AVSS2
P113/ANI11
P112/ANI10
P111/ANI9
P110/ANI8
P77/ANI7
Notes 1. Under development
2. Pins SCL and SDA are provided for the µPD784928Y subseries only.
Caution Directly connect the IC (Internally Connected) pins to VSS in the normal operation mode.
Data Sheet U12255EJ2V0DS00
5
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