UPD784054 Datasheet PDF - NEC
| Part Number | UPD784054 | |
| Description | 16-BIT SINGLE-CHIP MICROCONTROLLER | |
| Manufacturers | NEC | |
| Logo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784054(A)
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD784054(A) is a product of the 78K/IV series, and based on the µPD784044(A) with the real-time output
function and two units of timers/counters deleted and a standby function invalid mode provided. A stricter quality
assurance program applies to the µPD784054(A) compared to the µPD784054 (standard model).
The µPD784054(A) is provided with many peripheral hardware functions such as ROM, RAM, I/O port, 10-bit
resolution A/D converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance
CPU.
Moreover, a flash memory model, µPD78F4046Note, that can operate on the same supply voltage as the mask ROM
model, and many development tools are under development.
Note Use for functional evaluation only.
The functions are described in detail in the following User’s Manuals. Be sure to read these manuals when
designing your system.
µPD784054 User’s Manual - Hardware : U11719E
78K/IV Series User’s Manual - Instruction : U10905E
FEATURES
• Higher reliability compared to the µPD784054
• Minimum instruction execution time
: 160 ns (with 12.5-MHz internal clock) ··· µPD784054(A)
200 ns (with 10-MHz internal clock) ··· µPD784054(A1), (A2)
• I/O port
: 64 lines
• Timer
: 16-bit timer × 3 units
• A/D converter
: 10-bit resolution × 16 channels
• Serial interface UART/IOE (3-wire serial I/O) : 2 channels
• Watchdog timer
: 1 channel
• Standby function HALT/STOP/IDLE/standby function invalid mode
• Supply voltage
: VDD = 4.5 to 5.5 V
APPLICATION FIELDS
Automotive appliances, etc.
In this document, in addition to the µPD784054(A), the µPD784054(A1) and 784054(A2) are also explained.
However, unless otherwise specified, the µPD784054(A) is treated as the representative model throughout
this document.
The information in this document is subject to change without notice.
Document No. U13122EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
1998
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CONTENTS
µPD784054(A)
1. DIFFERENCES BETWEEN µPD784054(A) AND µPD784044(A), 784046(A) ................................. 7
2. PIN CONFIGURATION (Top View) ..................................................................................................... 8
3. SYSTEM CONFIGURATION EXAMPLE ...........................................................................................10
4. BLOCK DIAGRAM ............................................................................................................................. 11
5. PIN FUNCTIONS ................................................................................................................................12
5.1 Port Pins .................................................................................................................................................... 12
5.2 Pins Other Than Port Pins ...................................................................................................................... 14
5.3 I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16
6. CPU ARCHITECTURE .......................................................................................................................18
6.1 Memory Space .......................................................................................................................................... 18
6.2 CPU Registers ........................................................................................................................................... 20
6.2.1 General-purpose registers ............................................................................................................. 20
6.2.2 Control registers ............................................................................................................................. 21
6.2.3 Special function registers (SFRs) .................................................................................................. 22
7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................27
7.1 Ports ........................................................................................................................................................... 27
7.2 Clock Generation Circuit ......................................................................................................................... 28
7.3 Timer .......................................................................................................................................................... 30
7.4 A/D Converter ........................................................................................................................................... 32
7.5 Serial Interface .......................................................................................................................................... 33
7.5.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 34
7.6 Edge Detection Circuit ............................................................................................................................ 36
7.7 Watchdog Timer ........................................................................................................................................ 36
8. INTERRUPT FUNCTION....................................................................................................................37
8.1 Interrupt Source ....................................................................................................................................... 37
8.2 Vectored Interrupt .................................................................................................................................... 39
8.3 Context Switching .................................................................................................................................... 40
8.4 Macro Service ........................................................................................................................................... 41
9. LOCAL BUS INTERFACE .................................................................................................................44
9.1 Memory Expansion .................................................................................................................................. 45
9.2 Memory Space .......................................................................................................................................... 46
9.3 Programmable Wait .................................................................................................................................. 46
9.4 Bus Sizing Function ................................................................................................................................. 46
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| Information | Total 30 Pages | |
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