UPD77111F1 Datasheet PDF - NEC
| Part Number | UPD77111F1 | |
| Description | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS | |
| Manufacturers | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77110, 77111, 77112
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
DESCRIPTION
The µPD77110, 77111, and 77112 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the µPD77016 family, these DSPs have improved power consumption and are ideal for battery-
powered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µPD77111 Family User’s Manual
: To be available soon
µPD7701X Family User’s Manual - Instructions: U13116E
FEATURES
z Instruction cycle (operating clock)
µPD77110 : 15.3 ns MIN (65 MHz MAX)
13.3 ns MIN (75 MHz MAX) (Operating voltage and ambient temperature are limited.)
µPD77111 : 13.3 ns MIN (75 MHz MAX)
µPD77112 : 13.3 ns MIN (75 MHz MAX)
z Memory
• Internal instruction memory
µPD77110 : RAM 35.5K words × 32 bits
µPD77111 : RAM 1K words × 32 bits
Mask ROM 31.75K words × 32 bits
µPD77112 : RAM 1K words × 32 bits
Mask ROM 31.75K words × 32 bits
• Data memory
µPD77110 : RAM 24K words × 16 bits × 2 banks
External memory space 32K words × 16 bits × 2 banks
µPD77111 : RAM 3K words × 16 bits × 2 banks
Mask ROM 16K words × 16 bits × 2 banks
µPD77112 : RAM 3K words × 16 bits × 2 banks
Mask ROM 16K words × 16 bits × 2 banks
External memory space 16K words × 16 bits × 2 banks
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12801EJ4V0DS00 (4th edition)
Date Published November 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1998, 1999
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DSP FUNCTION LIST
Item µPD77016
Memory space Internal instruction RAM
(words × bits) Internal instruction ROM
1.5K × 32
None
Data RAM
(X/Y memory)
2K × 16 each
µPD77018A µPD77019 µPD77019-013 µPD77110
256 × 32
4K × 32
35.5K × 32
24K × 32
None
3K × 16 each
24K × 16 each
µPD77111
µPD77112
1K × 32
31.75K × 32
3K × 16 each
µPD77113 µPD77114
3.5K × 32
48K × 32
16K × 16 each
Data ROM
(X/Y memory)
None
12K × 16 each
None
16K × 16 each
32K × 16 each
External instruction
memory
48K × 32
None
External data memory 48K × 16 each
(X/Y memory)
16K × 16 each
32K × 16 each
None
16K × 16 each
None
8K × 16 each
Instruction cycle (at maximum speed) 30 ns (33 MHz)
Multiple
–
16.6 ns (60 MHz)
15.3 ns (65 MHz)
×1, 2, 3, 4, 8 (mask option)
Fixed to ×4 Integer of ×1 to 8
(external pin)
13.3 ns (75 MHz)
Integer of ×1 to 16 (mask option)
Serial interface (two channels)
Channels 1 and 2 Channel 1 has same function as µPD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).
have same function.
Supply voltage
5V
3V
DSP core: 2.5 V
I/O pins : 3 V
Package
160-pin QFP 100-pin TQFP
116-pin BGA
100-pin TQFP
80-pin TQFP 100-pin TQFP 80-pin FBGA 100-pin TQFP
80-pin FBGA
Preview 5 Page |
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UPD77111F1.PDF Datasheet ] | |
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