PDF UPD72870AGM-8ED Data sheet ( Hoja de datos )

Número de pieza	UPD72870AGM-8ED
Descripción	IEEE1394 1-CHIP OHCI HOST CONTROLLER
Fabricantes	NEC
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No Preview Available ! PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD72870A IEEE1394 1-CHIP OHCI HOST CONTROLLER The µPD72870A is the LSI which integrated OHCI-Link and PHY function into a single chip. The µPD72870A complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up to 400 Mbps. It makes design so compact for PC and PC card application. FEATURES • Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 • Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) • Numbers of supported port (1, 2, 3 ports) are selectable • Compliant with protocol enhancement as defined in P1394a draft 2.0 • Modular 32-bit host interface compliant to PCI Specification release 2.1 • Support PCI-Bus Power Management Interface Specification release 1.0 • Modular 32-bit host interface compliant to Card Bus Specification • Cycle Master and Isochronous Resource Manager capable • Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) • 32-bit CRC generation and checking for receive/transmit packets • 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported • 32-bit DMA channels for physical memory read/write • Clock generation by 24.576 MHz X’tal • Internal control and operational registers direct-mapped to PCI configuration space • 2-wire Serial EEPROMTM interface supported • Separate power supply Link and PHY • Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1) ORDERING INFORMATION Part number µPD72870AGM-8ED µPD72870AF1-FA2 Package 160-pin plastic LQFP (Fine pitch) (24 x 24) 192-pin plastic FBGA (14 x 14) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14653EJ1V0DS00 (1st edition) Date Published January 2000 NS CP (K) Printed in Japan 2000 1 page Link Block Diagram µPD72870A Serial ROM Interface PCI Controller Interface (Master, Parity Check & Generator) PCI-DMA IOREG CSR (CIS) PFCOMM Buf Byte Swap OPCI Internal Bus PCIS_CNT PCIS Bus (PCI Slave Bus) PCICFG ATDMA PAU OPCIBUS_ARB GRSU GRQU ITDMA IRDMA0- IRDMA3 SFIDU Byte Swap ATF Byte Swap ITF ITCF RF Byte Swap RCF Link Layer Core IOREG ATDMA ATF CIS CSR IOREG IRDMA ITCF ITDMA ITF OPCIBUS_ARB PAU PCICFG PCIS_CNT PFCOMM RCF RF SFIDU : Asynchronous Transmit DMA : Asynchronous Transmit FIFO : CIS Register : Control and Status Registers : IO Registers : Isochronous Receive DMA : Isochronous Transmit Control FIFO : Isochronous Transmit DMA : Isochronous Transmit FIFO : OPCI Internal Bus Arbitration : Physical Response and Request Unit : PCI Configuration Registers : PHY Control Isochronous Control : Pre Fetch Command FIFO : Receive Control FIFO : Receive FIFO : Self-ID DMA Preliminary Data Sheet S14653EJ1V0DS00 5 5 Page µPD72870A 4. PHY FUNCTION .................................................................................................................................... 33 4.1 Cable Interface ............................................................................................................................... 33 4.1.1 Connections.......................................................................................................................................... 33 4.1.2 Cable Interface Circuit .......................................................................................................................... 34 4.1.3 CPS....................................................................................................................................................... 34 4.1.4 Unused Ports ........................................................................................................................................ 34 4.2 Suspend/Resume........................................................................................................................... 35 4.2.1 Suspend/Resume On Mode (SUS_RESM = 1)..................................................................................... 35 4.2.2 Suspend/Resume Off Mode (SUS_RESM = 0)..................................................................................... 35 4.3 PLL and Crystal Oscillation Circuit.............................................................................................. 36 4.3.1 Crystal Oscillation Circuit...................................................................................................................... 36 4.3.2 PLL ....................................................................................................................................................... 36 4.4 PC0-PC2, CMC................................................................................................................................ 36 4.5 P_RESETB ...................................................................................................................................... 36 4.6 RI0, RI1 ............................................................................................................................................ 36 5. SERIAL ROM INTERFACE .................................................................................................................. 37 5.1 Serial EEPROM Register ............................................................................................................... 37 5.2 Serial EEPROM Register Description .......................................................................................... 37 5.3 Load Control................................................................................................................................... 42 5.4 Programming Sequence Example................................................................................................ 42 6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 44 7. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 47 8. PACKAGE DRAWINGS ........................................................................................................................ 48 Preliminary Data Sheet S14653EJ1V0DS00 11 11 Page

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