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PDF UPD72862GC-9EU Data sheet ( Hoja de datos )
| Número de pieza | UPD72862GC-9EU | |
| Descripción | IEEE1394 OHCI HOST CONTROLLER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72862
IEEE1394 OHCI HOST CONTROLLER
The µPD72862 is IEEE1394 OHCI-Link controller. The µPD72862 complies with the P1394a draft 2.0
specifications and works up to 400 Mbps.
It supports both of the Cardbus interface and the PCI bus interface.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
• Compliant with protocol enhancement as defined in P1394a draft 2.0
• Modular 32-bit host interface compliant to PCI Specification release 2.1
• Supports PCI-Bus Power Management Interface Specification release 1.0
• Supports Cardbus
• Equipped CIS register
• Cycle Master and Isochronous Resource Manager capable
• Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface
• Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048
bytes)
• 32-bit CRC generation and checking for receive/transmit packets
• 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported
• Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY
• Internal control and operational registers direct-mapped to PCI configuration space
• 2-wire Serial EEPROMTM interface supported
ORDERING INFORMATION
Part number
Package
µPD72862GC-9EU
100-pin plastic TQFP (Fine pitch) (14 x 14)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14265EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
1999
1 page  
PIN NAME
AD0-AD31
CARD_ON
CBE0-CBE3
CIS_ON
CLKRUN
CTL0, CTL1
DEVSEL
DIRECT
D0-D7
FRAME
GNT
GROM_EN
GROM_SCL
GROM_SDA
IC (H)
IC (L)
IDSEL
INTA
IRDY
LINKON
LPS
LREQ
NC
PAR
PCLK
PERR
PIN_EN
PME
PRST
REQ
SCLK
SERR
STOP
TRDY
VDD
VSS
: PCI Multiplexed Address and Data
: PCI/Card Select
: Command/Byte Enables
: CIS Register ON
: PCICLK Running
: PHY/Link Bi-directional Control
: Device Select
: Auxiliary PHY/Link Signal
: PHY/Link Bi-directional Data
: Cycle Frame
: Bus_master Grant
: Serial EEPROM Enable
: Serial EEPROM Clock Output
: Serial EEPROM Data Input / Output
: Internally Connected (High Clamped)
: Internally Connected (Low Clamped)
: ID Select
: Interrupt
: Initiator Ready
: Link-On Request
: Link Power Status
: PHY/Link Request
: Non-Connection
: Parity
: PCI Clock
: Parity Error
: Pin Enable Input
: PME Output
: Reset
: Bus_master Request
: PHY Clock
: System Error
: PCI Stop
: Target Ready
: Supply Voltage
: Ground
µPD72862
Data Sheet S14265EJ2V0DS00
5
5 Page 
µPD72862
2. REGISTER DESCRIPTIONS
2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )
31 24 23 16 15 08 07 00
DeviceID
VendorID
00H
Status
Command
04H
Class Code
Revision ID
08H
BIST
Header Type
Latency Timer
Cache Line Size
0CH
Base Address 0 (OHCI Registers)
10H
Base Address 1
14H
Base Address 2
18H
Base Address 3
1CH
Base Address 4
20H
Base Address 5
24H
CardBus CIS Pointer
28H
Subsystem ID
Subsystem Vendor ID
2CH
Expansion Rom Base Address Register
30H
000000H
Cap_Ptr
34H
00000000H
38H
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
3CH
PCI_OHCI_Control
40H
00000000H
44H
00000000H
48H
00000000H
4CH
Diagnostic register0
50H
Diagnostic register1
54H
Diagnostic register2
58H
Diagnostic register3
5CH
Power Management Capabilities
Next_Item_Ptr
Cap_ID
60H
Data
PMCSR_BSE
Power Management Control/Status
64H
00000000H
68H
00000000H
6CH
User Area (GENERAL_RegisterA)
70H
User Area (GENERAL_RegisterB)
74H
User Area (GENERAL_RegisterC)
78H
User Area (GENERAL_RegisterD)
7CH
00000000H
80H
FCH
Data Sheet S14265EJ2V0DS00
11
11 Page | ||
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| PDF Descargar | [ Datasheet UPD72862GC-9EU.PDF ] | |
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