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PDF uPD72107CW Data sheet ( Hoja de datos )
| Número de pieza | uPD72107CW | |
| Descripción | LAP-B CONTROLLER(Link Access Procedure Balanced mode) | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72107
LAP-B CONTROLLER
Link Access Procedure Balanced mode
The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
FEATURES
• Complied with ITU-T recommended X.25 (LAP-B84
edition)
HDLC frame control
Sequence control
Flow control
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
Option frame
Global address frame
Error check deletion frame
• Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
• Memory-based interface
Memory-based command
Memory-based status
Memory-based transmit/receive data
• MAX.4 Mbps serial transfer rate
• NRZ, NRZI coding
ORDERING INFORMATION
Part Number
µPD72107CW
µPD72107GC-3B9
µPD72107L
Package
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
The information in this document is subject to change without notice.
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
©
1998
1 page  
68-pin plastic QFJ (950 × 950 mils)
µPD72107L
µPD72107
RESET
IC
B/W
PU
CLK
GND
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLRINT
INT
UBE
MWR
MRD
GND
IOWR
IORD
CS
VCC
VCC
D7
D6
D5
D4
D3
D2
5
5 Page 
µPD72107
Pin Name
SDIP
QFP
QFJ
Active
I/O
Pin No. Pin No. Pin No.
Level
Function
RxD
3 14 4
I – A serial receive data input pin.
(Receive Data)
RxC
2 13 3
I – When CLK is set to 01 or 10 by “operation mode
(Receive Clock)
setting LCW”
Sixteen times the clock input of the transmit/receive
clock for the on-chip DPLL of the µPD72107
When CLK is set to 00 by “operation mode setting
LCW”
One time the clock input of the receive clock
Remark LCW: abbreviation for Link Command Word
1.2 Pin Status after Reset of µPD72107
The status of the output pins and input/output pins after reset in the µPD72107 is as shown in Table 1-1.
Table 1-1. Pin Status after Reset
64-pin SDIP
4
5
15, 16
17 to 30
31 to 38
39 to 46
52
53
54
55
57
60
61
64
Note 3-state
Pin Number
80-pin QFP
16
17
30, 31
32 to 47
(except 40, 41)
48 to 58
(except 50, 51, 55)
59 to 67
(except 61)
75
76
77
78
2
5
6
10
68-pin QFJ
6
7
17, 18
19 to 32
33 to 41
(except 35)
42 to 49
56
57
58
59
61
64
65
68
Pin Name
TxC
TxD
A0, A1
A2 to A15
I/O
I/ONote
O
I/ONote
ONote
During Reset
High impedance
H
High impedance
High impedance
A16D8 to A23D15
I/ONote
High impedance
D0 to D7
I/ONote High impedance
MRD
MWR
UBE
INT
HLDRQ
ASTB
AEN
RTS
ONote
ONote
I/ONote
O
O
O
O
O
High impedance
High impedance
High impedance
L
L
L
L
H
Remarks 1. The status after reset is released is the same as the status during reset.
2. Input low level to the RESET pin for more than 7 clocks of the system clock.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet uPD72107CW.PDF ] | |
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