PDF UPD70433 Data sheet ( Hoja de datos )

Número de pieza	UPD70433
Descripción	V55PITM 16-BIT MICROPROCESSOR
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS INTEGRATED CIRCUIT µPD70433 V55PITM 16-BIT MICROPROCESSOR DESCRIPTION The µPD70433 (V55PI) is a microprocessor in which a 16-bit CPU, RAM, serial interface, parallel interface, A/D converter, timers, DMA controller, interrupt controller, etc., are integrated in a single chip. The V55PI is software-compatible with the µPD70320 and 70330 (V25TM and V35TM) single-chip microcontrollers. The V55PI provides a migration path from the V25. It offers higher-level functions and higher performance, and is particularly suitable for control of data processing systems associated with mechanical control, including printer and facsimile. Detailed functions are described in the following user’s manuals, which should be read when carrying out design work. • V55PI User’s Manual Hardware : U10514E • V55PI User’s Manual Instruction : U10231E FEATURES • Internal 16-bit architecture, selectable external data bus width (16/8 bits) • Software compatible with V20TM and V30TM (native mode) and V25 and V35 (includes additional instructions) • Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz) 125 ns/16 MHz (external 32 MHz) • Address space: 16M bytes: 1-Mbyte basic memory space 16-Mbyte extended memory space • Register file space (in on-chip RAM) : 512 bytes/16 register banks • I/O space : 64K bytes • Automatic wait control with memory space divided in variable sizes (max. 6 blocks) • I/O line (input ports: 11 bits, input/output ports: 42 bits) • DMA controller (DMAC): Max. 4-channel configuration possible • Four DMA transfer modes (single transfer, demand release, single step, burst) • Intelligent DMA modes 1 and 2 • Serial interface: 2 channels • Asynchronous mode (UART) or clocked mode (CSI) selectable • Parallel interface: 8 bits • Centronics data input/output and general-purpose data input/output • A/D converter (8 bits): 4 channels • Real-time output port: 4 bits × 2 channels or 8 bits × 1 channel • PMW (Pulse Width Modulation) output function : 8 bits The information in this document is subject to change without notice. Document No. U11775EJ4V0DS00 (4th edition) Previous No. IC-8257 Date Published November 1996 P Printed in Japan The mark shows major revised points. © 1995 1 page µPD70433 No. Signal Nane F1 RTPT7 F2 RTPT6 F3 RTPT4 F12 ––– F13 ––– F14 ––– G1 NC G2 DMARQ0 G3 VDD G12 ––– G13 ––– G14 ––– H1 DMARQ1 H2 DMAAK0 H3 DMAAK1 H12 REFRQ H13 ––– H14 NC J1 TCE0 J2 TCE1 J3 GND J12 VDD J13 X2 J14 GND K1 VDD K2 IC (H) Port No. Signal Name P77 K3 AD2 P76 K12 POLL P74 K13 WDTOUT P07 K14 X1 P05 L1 AD0 P04 L2 AD3 ––– L3 AD6 P80 L12 BUSLOCK ––– L13 READY P03 L14 RESET P02 M1 AD1 P01 M2 AD5 P81 M3 NC ––– M4 AD8 ––– M5 AD12 ––– M6 A16 P00 M7 A20 ––– M8 VDD ––– M9 WRH ––– M10 IORD ––– M11 NC ––– M12 NC ––– M13 HLDAK ––– M14 CLKOUT ––– N1 AD4 ––– N2 NC Port No. Signal Name ––– N3 AD9 ––– N4 AD11 ––– N5 AD14 ––– N6 A18 ––– N7 A21 ––– N8 A23 ––– N9 D8/D16 ––– N10 ASTB ––– N11 IOWR ––– N12 DEX ––– N13 VDD ––– N14 HLDRQ ––– P1 AD7 ––– P2 AD10 ––– P3 AD13 ––– P4 AD15 ––– P5 A17 ––– P6 A19 ––– P7 NC ––– P8 A22 ––– P9 GND ––– P10 IC (L) ––– P11 WRL ––– P12 RD ––– P13 RAS ––– P14 OPEN Port ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Remark IC: Internally Connected NC: Non-Connection Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 kΩ). 2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 kΩ). 3. No connection should be made to the OPEN pin. 5 5 Page µPD70433 1.1.2 Non-Port Pins (1) Bus control pins Pin Name ASTB RD WRL WRH READY DEX RAS D8/D16 BUSLOCK POLL HLDRQ HLDAK REFRQ AD0 to AD15 A16 to A23 IORD IOWR DMARQ0 DMARQ1 DMAAK0 DMAAK1 TCE0 TCE1 Input/ Output Function External bus cycle address strobe signal output in external bus Output External memory cycle data read strobe signal output in external bus External memory cycle lower byte data write strobe signal output in external bus External memory cycle upper byte data write strobe signal output in external bus Input External bus cycle ready signal input in external bus Output External bus cycle upper byte data enable signal output DRAM low address latch timing signal output Input External bus data bus width selection signal input Output External bus bus lock signal output Input Input of POLL signal (sampled in POLL instruction execution) External bus hold request signal input Output External bus hold acknowledge signal output Refresh pulse signal output 3–state External bus cycle address/data multiplex signal input/output input/output in external bus 3–state output External bus cycle address signal output in external bus Output External I/O cycle data read strobe signal output External I/O cycle data write strobe signal output Input DMA request signal input (channel 0) DMA request signal input (channel 1) DMA acknowledge signal output (channel 0) Output DMA acknowledge signal output (channel 1) DMA termination signal output (channel 0) DMA termination signal output (channel 1) Alternate Function ––– P80 P81 ––– 11 11 Page

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