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PDF 10KE Data sheet ( Hoja de datos )
| Número de pieza | 10KE | |
| Descripción | Embedded Programmable Logic Device | |
| Fabricantes | Altera Corporation | |
| Logotipo |  |
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January 2003, ver. 2.5
®
FLEX 10KE
Embedded Programmable
Logic Device
Data Sheet
Features...
f
■ Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic array for general logic functions
■ High density
– 30,000 to 200,000 typical gates (see Tables 1 and 2)
– Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used without reducing logic capacity
■ System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
– Low power consumption
– Bidirectional I/O performance (tSU and tCO) up to 212 MHz
– Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at
33 MHz or 66 MHz
– -1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2, for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the
FLEX 10K Embedded Programmable Logic Family Data Sheet.
Table 1. FLEX 10KE Device Features
Feature
Typical gates (1)
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-F10KE-2.5
EPF10K30E
30,000
119,000
1,728
6
24,576
220
EPF10K50E
EPF10K50S
50,000
199,000
2,880
10
40,960
254
1
1 page  
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 5. FLEX 10KE Performance
Application
Resources Used
Performance
Units
LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade
16-bit loadable counter
16 0
285
250
200 MHz
16-bit accumulator
16 0
285
250
200 MHz
16-to-1 multiplexer (1)
10 0
3.5
4.9
7.0 ns
16-bit multiplier with 3-stage 592
0
156
131
93 MHz
pipeline (2)
256 × 16 RAM read cycle
01
196
154
118 MHz
speed (2)
256 × 16 RAM write cycle
01
185
143
106 MHz
speed (2)
Notes:
(1) This application uses combinatorial inputs and outputs.
(2) This application uses registered inputs and outputs.
Table 6 shows FLEX 10KE performance for more complex designs. These
designs are available as Altera MegaCore® functions.
Table 6. FLEX 10KE Performance for Complex Designs
Application
LEs Used
Performance
Units
8-bit, 16-tap parallel finite impulse
response (FIR) filter
8-bit, 512-point fast Fourier
transform (FFT) function
a16450 universal asynchronous
receiver/transmitter (UART)
597
1,854
342
-1 Speed Grade -2 Speed Grade -3 Speed Grade
192 156 116 MSPS
23.4
113
36
28.7
92
28
38.9
68
20.5
µs (1)
MHz
MHz
Note:
(1) These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks
required = ceiling [log 2 (points)/2] × [points +14 + ceiling]
Altera Corporation
5
5 Page 
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous read or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see Figure 2).
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Notes (1)
Row Interconnect
data[ ]
24
rdaddress[ ]
EAB Local
Interconnect (2)
wraddress[ ]
rden
wren
outclocken
DQ
ENA
DQ
ENA
DQ
ENA
DQ
ENA
RAM/ROM
256 × 16
Data
In
512
1,024
×
×
8
4
2,048 × 2
Data Out
Read Address
4, 8, 16, 32
DQ
ENA
4, 8
Write Address
Read Enable
Write Enable
4, 8, 16, 32
inclocken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Column Interconnect
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
Altera Corporation
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 10KE.PDF ] | |
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