PDF IDT72520 Data sheet ( Hoja de datos )

Número de pieza	IDT72520
Descripción	BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
Fabricantes	Integrated Device Technology
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BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT IDT72510 IDT72520 FEATURES: • Two side-by-side FIFO memory arrays for bidirectional data transfers • 512 x 18-Bit – 1024 x 9-Bit (IDT72510) • 1024 x 18-Bit – 2048 x 9-Bit (IDT72520) • 18-bit data bus on Port A side and 9-bit data bus on Port B side • Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18- bit communication • Fast 25ns access time • Fully programmable standard microprocessor interface • Built-in bypass path for direct data transfer between two ports • Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO • Two programmable flags, Almost-Empty and Almost-Full for each FIFO • Programmable flag offset can be set to any depth in the FIFO • Any of the eight internal flags can be assigned to four external flag pins • Flexible reread/rewrite capabilities. • On-chip parity checking and generation • Standard DMA control pins for data exchange with peripherals • IDT72510 and IDT72520 available in the the 52-pin PLCC package DESCRIPTION: The IDT72510 and IDT72520 are highly integrated first- in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. The BiFIFOs incorporate bus matching logic to convert the 18-bit wide memory data paths to the 9-bit wide Port B data bus. The BiFIFOs have a bypass path that allows the device con- nected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFOs have programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight inter- nal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has parity, reread/rewrite and DMA functions. Par- ity generation and checking can be done by the BiFIFO on data passing through Port B. The Reread and Rewrite con- SIMPLIFIED BLOCK DIAGRAM 18-Bit FIFO 18-bits Data Bypass Path 9-bits 9-bits Data Port A 18-Bit FIFO Port B Control Processor Interface A Registers Processor Interface B Flags Programmable Flag Logic The IDT logo is a registered trademark of Integrated Device Techology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.31 Handshake Interface Control DMA 2669 drw 01 DECEMBER 1995 DSC-2669/- 1 1 page IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO DETAILED BLOCK DIAGRAM COMMERCIAL TEMPERATURE RANGE 5.31 2669 drw 03 5 5 Page IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE RESET COMMAND FUNCTIONS Reset Operands Function 000 No Operation 001 Reset B→A FIFO (Read, Write, and Rewrite Pointers = 0) 010 Reset A→B FIFO (Read, Write, and Reread Pointers = 0) 011 Reset B→A and A→B FIFO 100 Reset Internal DMA Request Circuitry 101 No Operation 110 No Operation 111 Reset All Table 3. Reset Command Functions 2669 tbl 06 6420H, and Configuration Registers 5 and 7 are 0000H. Additionally, Status Register format 0 is selected, all the pointers including the Reread and Rewrite Pointers are set to 0, the odd byte register valid bit is cleared, the DMA direction is set to B→A write, the internal DMA request circuitry is cleared (set to its initial state), and all parity errors are cleared. A software reset command can reset A→B pointers and the B→A pointers to 0 independently or together. The request (REQ) DMA circuitry can also be reset independently. A software Reset All command resets all the pointers, the DMA request circuitry, and sets all the Configuration Registers to their default condition. Note that a hardware reset is NOT the same as a software Reset All command. Table 7 shows the BiFIFO state after the different hardware and software resets. SELECT CONFIGURATION REGISTER COMMAND FUNCTIONS Operands Function 000 Select Configuration Register 0 001 Select Configuration Register 1 010 Select Configuration Register 2 011 Select Configuration Register 3 100 Select Configuration Register 4 101 Select Configuration Register 5 110 Select Configuration Register 6 111 Select Configuration Register 7 2669 tbl 07 Table 4. Select Configuration Register Command Functions. DMA DIRECTION COMMAND FUNCTIONS Operands Function XX0 Write B→A FIFO XX1 Read A→B FIFO 2669 tbl 08 Table 5. Set DMA Direction Command Functions. Command Only Operates in Peripheral Interface Mode STATUS REGISTER FORMAT COMMAND FUNCTIONS Operands Function XX0 Status Register Format 0 XX1 Status Register Format 1 2669 tbl 09 Table 6. Command Functions to Set the Status Register Format STATE AFTER RESET Configuration Registers 0-3 Configuration Register 4 Configuration Register 5 Configuration Register 7 Status Register format B→A Read, Write, Rewrite Pointers A→B Read, Write, Reread Pointers Odd byte register valid bit DMA direction DMA internal request Parity errors Hardware Reset (RS asserted) 0000H 6420H 0000H 0000H 0 0 B→ A (001) — — — — — 0 Software Reset A→B (010) B→A and A→B (011) —— —— —— —— —— —0 Internal Request (100) — — — — — — 0 —0 0— clear B→ A write clear clear clear — clear — ———— — — — clear ———— Table 7. The BiFIFO State After a Reset Command All (111) 0000H 6420H 0000H 0000H — 0 0 clear — clear — 2669 tbl 10 5.31 11 11 Page

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