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PDF IDT72402 Data sheet ( Hoja de datos )
| Número de pieza | IDT72402 | |
| Descripción | CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
CMOS PARALLEL FIFO
64 x 4-BIT AND 64 x 5-BIT
IDT72401
IDT72402
IDT72403
IDT72404
FEATURES:
• First-ln/First-Out Dual-Port memory
• 64 x 4 organization (IDT72401/03)
• 64 x 5 organization (IDT72402/04)
• IDT72401/02 pin and functionally compatible with
MMI67401/02
• RAM-based FIFO with low falI-through time
• Low-power consumption
— Active: 175mW (typ.)
• Maximum shift rate — 45MHz
• High data output drive capability
• Asynchronous and simultaneous read and write
• Fully expandable by bit width
• Fully expandable by word depth
• IDT72403/04 have Output Enable pin to enable output
data
• High-speed data communications applications
• High-performance CMOS technology
• Available in CERDIP, plastic DIP and SOIC
• Military product compliant to MlL-STD-883, Class B
• Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-
performance First-ln/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-ln/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data
at the data input (D0-D3, 4). The stored data stack up on a first-
in/first-out basis.
A Shift Out (SO) signal causes the data at the next to last
word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The
Input Ready signal can also be used to cascade multiple
devices together. The Output Ready (OR) signal is a flag to
indicate that the output remains valid data (OR = HIGH) or to
indicate that the FIFO is empty (OR = LOW). The Output
Ready can also be used to cascade multiple devices together.
Width expansion is accomplished by logically ANDing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.
Depth expansion is accomplished by tying the data inputs
of one device to the data outputs of the previous device. The
Input Ready pin of the receiving device is connected to the
Shift Out pin of the sending device and the Output Ready pin
of the sending device is connected to the Shift In pin of the
receiving device.
Reading and writing operations are completely asynchro-
nous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FlFOs ideal for high-speed
communication and controller applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SI INPUT
CONTROL
IR LOGIC
D 0-3
D4
(IDT72402
and IDT72404)
MR
DATA IN
MASTER
RESET
WRITE POINTER
WRITE MULTIPLEXER
MEMORY
ARRAY
READ MULTIPLEXER
READ POINTER
OUTPUT
ENABLE
DATA OUT
OUTPUT
CONTROL
LOGIC
OE (IDT72403 and
IDT72404)
Q 0-3
Q 4 (IDT72402 and
IDT72404)
SO
OR
2747 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.01
SEPTEMBER 1996
DSC-2747/7
1
1 page  
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Output
Data is shifted out on the HlGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be
advanced to the next word location. If data is present, valid
data will appear on the outputs and Output Ready (OR) will
go HIGH. If data is not present, Output Ready will stay
LOW indicating the FIFO is empty. The last valid word read
from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty, Output Ready (OR) goes LOW
on the LOW-to-HIGH transition of Shift Out. Previous data
remains on the output until the HIGH-to-LOW transition of
Shift Out (SO).
Fall-Through Mode
The FIFO operates in a fall-through mode when data gets
shifted into an empty FIFO. After a fall-through delay the data
propagates to the output. When the data reaches the output,
the Output Ready (OR) goes HIGH. Fall-through mode also
occurs when the FIFO is completely full. When data is shifted
out of the full FIFO, a location is available for new data. After
a fall-through delay, the Input Ready goes HIGH. If Shift In is
HIGH, the new data can be written to the FIFO.
Since these FlFOs are based on an internal dual-port RAM
architecture with separate read and write pointers, the fall-
through time (tPT) is one cycle long. A word may be written
into the FIFO on a clock cycle and can be accessed on the next
clock cycle.
TIMING DIAGRAMS
SHIFT IN
INPUT READY
INPUT DATA
tSIH
t IDH
t IDS
1/fIN
t SIL
1/fIN
tIRH
tIRL
Figure 2. Input Timing
2747 drw 07
(7)
SHIFT IN
(2)
INPUT READY
(1)
(4)
(3)
INPUT DATA
STABLE DATA
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the first word.
3. Input Ready goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
(5)
(6)
2747 drw 08
5.01 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT72402.PDF ] | |
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| IDT72403 | CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT | Integrated Device Technology |
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