74112 Datasheet PDF - STMicroelectronics
Part Number | 74112 | |
Description | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | |
Manufacturers | STMicroelectronics | |
Logo | ||
There is a preview and 74112 download ( pdf file ) link at the bottom of this page. Total 11 Pages |
Preview 1 page No Preview Available ! M54HC112
M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 67 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS112
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 11 2F 1R
M 74H C1 12 M1 R
M 74HC 11 2B 1R
M 74H C1 12 C1 R
The M54/74HC112 is a high speed CMOS DUAL J-K
FLIP-FLOP WITH PRESET AND CLEAR fabricated in
silicon gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption. The
M54HC112/M74HC112 dual JK flip-flop features indi-
vidual J,K, clock, and asynchronous set and clearinputs
for each flip-flop. When the clock goes high, the inputs
are enabled and data will be accepted. The logic level
of the J and K inputs may be allowed to change when
the clock pulse is high and the bistable will function as
shown in the truth table. Input data is transferred to the
input on the negative going edge of the clock pulse. All
inputs are equipped withprotection circuits against static
discharge and transient excess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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M54/M74HC112
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(CK - Q, Q)
2.0
4.5
6.0
52 125 155 190
16 25 31 38 ns
14 21 26 32
tPLH Propagation
2.0
tPHL Delay Time
4.5
(CLR, PR - Q, Q) 6.0
68 135 170 205
17 27 34 41 ns
14 23 29 35
fMAX Maximum Clock 2.0
Frequency
4.5
8 16
40 68
6.4 5.4
32 27 MHz
6.0 47 79 38 32
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0
4.5
6.0
20 75
5 15
4 13
95 110
19 22 ns
16 19
tW(L) Minimum Pulse
Width
(CLR, PR)
2.0
4.5
6.0
20 75
5 15
4 13
95 110
19 22 ns
16 19
ts Minimum Set-up 2.0
Time
4.5
28 75
7 15
95 110
19 22 ns
6.0 6 13 16 19
th Minimum Hold 2.0
Time
4.5
000
0 0 0 ns
6.0 0 0 0
tREM Minimum
Removal Time
(CLR, PR)
2.0
4.5
6.0
24 50 60 70
4 10 12 14 ns
39
10 12
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
33
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/2 (per FLIP/FLOP)
5/11
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 74112 electronic component. |
Information | Total 11 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ 74112.PDF Datasheet ] |
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