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7013 Datasheet PDF - Analog Devices

Part Number 7013
Description CMOS TIA IS-54 Baseband Receive Port
Manufacturers Analog Devices 
Logo Analog Devices Logo 

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7013 datasheet, circuit
a
CMOS
TIA IS-54 Baseband Receive Port
AD7013
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 µW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DxCLK
DATA IN
FRAME IN
MODE1
FRAME OUT
Rx CLK
Rx DATA
Rx FRAME
MCLK
DGND VDD
AUX DAC1 AUX DAC2 AUX DAC3
FS ADJUST VAA AGND
SERIAL
INTERFACE
RECEIVE
CHANNEL
SERIAL
INTERFACE
10-BIT
AUX DAC
8-BIT
AUX DAC
8-BIT
AUX DAC
FULL-SCALE
ADJUST
LATCH
LATCH
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
LATCH
1.23V
REFERENCE
AD7013
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
AGND
AGND
BYPASS
IRx
IRx
AUX IRx
AUX IRx
QRx
QRx
AUX QRx
AUX QRx
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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7013 equivalent
SSOP Pin
Number
Mnemonic
POWER SUPPLY
1 VAA
21 VDD
10, 25, 27
16
AGND
DGND
ANALOG SIGNAL AND REFERENCE
28 BYPASS
2, 4 IRx, IRx
6, 8 QRx, QRx
3, 5 AUX IRx, AUX IRx
7, 9 AUX QRx, AUX QRx
24
3, 22
26
AUX DAC1
AUX DAC2, AUX DAC3
FS ADJUST
SERIAL INTERFACE AND CONTROL
20 MCLK
19 DxCLK
17 FRAME IN
18 DATA IN
15 FRAME OUT
11 MODE1
RECEIVE INTERFACE AND CONTROL
14 RxCLK
12 RxFRAME
13 RxDATA
PIN FUNCTION DESCRIPTIONS
AD7013
Function
Positive Power Supply for Analog section. A 0.1 µF decoupling capacitor should be
connected between this pin and AGND.
Positive Power Supply for Digital section. A 0.1 µF decoupling capacitor should be
connected between this pin and DGND. Both VAA and VDD should be externally
tied together.
Analog Ground.
Digital Ground. Both AGND and DGND should be externally tied together.
Reference Decoupling Output. A 10 nF decoupling capacitor should be connected
between this pin and AGND.
Differential Analog Inputs for the I receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
Differential Analog Inputs for the Q receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
Auxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.
Auxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.
Analog output from the 10-bit auxiliary DAC.
Analog outputs from the 8-bit auxiliary DACs.
An external resistor is connected from this pin to ground to determine the full-
scale current for AUX DAC1, AUX DAC2, and AUX DAC3.
Master Clock, Digital Input. When operating in IS-54 Digital mode this pin should
be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock
source for Analog Mode.
Transmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which
can be used to clock the serial port of a DSP.
Digital Input. This is used to frame the clocking in of 16-bit words for the control
registers serial interface.
Digital Input. Transmit Serial Data, digital input. This pin is used to clock in
data for the serial interface on the rising edge of DxCLK.
Digital Output. This output represents a buffered version of FRAME IN and is
controlled by the MODE1 pin. This pin can be used to daisy chain the
FRAME IN signal.
Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high,
FRAME IN is buffered and made available on FRAME OUT.
When MODE1 is low, FRAME OUT is in 3-STATE.
Output Clock for the receive section interface.
Synchronization output for framing I and Q data at the receive interface.
Receive Data, digital output. I and Q data are available at this pin via a 16-bit serial
interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out
as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit
word is a I/Q flag bit, indicating whether that word is an I word or a Q word.
REV. A
–5–

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Information Total 20 Pages
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