PDF 74AC573B Data sheet ( Hoja de datos )

Número de pieza	74AC573B
Descripción	OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
Fabricantes	STMicroelectronics
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No Preview Available ! 74AC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s 50Ω TRANSMISSION LINE DRIVING BM CAPABILITY (Plastic Package) (Micro Package) s SYMMETRICAL OUTPUT IMPEDANCE: \|IOH\| = IOL = 24 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 s IMPROVED LATCH-UP IMMUNITY ORDER CODES : 74AC573B 74AC573M latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. DESCRIPTION While the (OE) input is low, the 8 outputs will be The AC573 is an advanced high-speed CMOS in a normal logic state (high or low logic level) OCTAL D-TYPE LATCH with 3 STATE OUTPUT andwww.DataSheet4U.com while high level the outputs will be in a high NON INVERTING fabricated with sub-micron impedance state. silicon gate and double-layer metal wiring C2MOS All inputs and outputs are equipped with technology. It is ideal for low power applications protection circuits against static discharge, giving mantaining high speed operation similar to them 2KV ESD immunity and transient excess equivalent Bipolar Schottky TTL. voltage. These 8 bit D-Type latches are controlled by a PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 1 page 74AC573 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symbol P ar ame te r tPLH Propagation Delay Time tPHL LE to Q tPLH Propagation Delay Time tPHL D to Q tPZL Output EnableTime tPZH tPLZ Output Disable Time tPHZ tw Clock Pulse Width HIGH or LOW ts Setup Time Q to CK HIGH or LOW th Hold Time Q to CK HIGH or LOW () Voltage range is 3.3V ± 0.3V () Voltage range is 5V ± 0.5V Test Condition V CC (V) 3.3() 5.0(*) 3.3() 5.0(*) 3.3() 5.0(*) 3.3() 5.0(*) 3.3() 5.0(*) 3.3() 5.0(*) 3.3() 5.0(**) Value TA = 25 oC -40 to 85 oC Min. Typ. Max. Min. Max. 6 10 12 4.5 8 9 5.5 10 12 4.5 8 9 6.5 11 13 59 10 7 12 14 6 10 11 1.5 4 4.5 1.5 3.5 4 0.5 3 3.5 0 2.5 3 -0.5 3 3.5 0 2.5 3 Unit ns ns ns ns ns ns ns CAPACITIVE CHARACTERISTICS Symbol P ar ame te r Test Conditions V CC (V) Value TA = 25 oC -40 to 85 oC Min. Typ. Max. Min. Max. Unit COUT Output Capacitance 5.0 8 pF CIN Input Capacitance 5.0 4 pF CPD Power Dissipation Capacitance (note 1) 5.0 20 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit) 5/10 5 Page

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74AC573B	OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING	STMicroelectronics
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