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PDF 74AC373M Data sheet ( Hoja de datos )
| Número de pieza | 74AC373M | |
| Descripción | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74AC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
BM
CAPABILITY
(Plastic Package)
(Micro Package)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
ORDER CODES :
74AC373B
74AC373M
tPLH ≅ tPHL
(OE).
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q
outputs will be latched precisely or inversely at
the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normal logic
DESCRIPTION
state (high or low logic level) and while high level
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technology. It is ideal for low power applications
mantaining high speed operation similar to All inputs and outputs are equipped with
equivalent Bipolar Schottky TTL.
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
These 8 bit D-Type latch are controlled by a latch voltage.
enable input (LE) and an output enable input
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
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1 page  
74AC373
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL LE to Q
tPLH Propagation Delay Time
tPHL D to Q
tPZL Output EnableTime
tPZH
tPLZ Output Disable Time
tPHZ
tw Clock Pulse Width HIGH
or LOW
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
6.5 12.0
14.0
5.0 9.5
10.5
6.5 12.0
14.0
5.0 9.5
10.5
7.0 11.0
13.0
5.0 8.5
9.5
7.5 12.0
13.0
6.5 9.0
10.0
1.5 5.5
6.0
1.5 4.0
4.5
0.5 5.5
6.0
0.5 4.0
4.5
-0.5 1.0
5.0
-0.5 1.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
COUT Output Capacitance
5.0
8 pF
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0
20 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74AC373M.PDF ] | |
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