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PDF 74AC280 Data sheet ( Hoja de datos )

Número de pieza 74AC280
Descripción 9 BIT PARITY GENERATOR
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



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No Preview Available ! 74AC280 Hoja de datos, Descripción, Manual

® 74AC280
9 BIT PARITY GENERATOR
s HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
BM
CAPABILITY
(Plastic Package)
(Micro Package)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
ORDER CODES :
74AC280B
74AC280M
odd/even parity outputs (ΣODD and ΣEVEN). The
nine data inputs control the output conditions.
When the number of high level input is odd,
ΣODD output is kept high and ΣEVEN output low.
Conservely, when the output is even, ΣEVEN
s IMPROVED LATCH-UP IMMUNITY
output is kept high and ΣODD low.
The IC generates either odd or even parity
DESCRIPTION
making it flexible application.
The
BIT
AC280 is
PARITY
anGaEdNvEaRncAeTdOhRigh-fsapberiecadteCdMOwSwwiwt9h.DataSheet4TcUa.hcosemcwadoirndg-.length
capability
is
easily
expanded
by
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
It is composed of nine data inputs (A to I) and
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
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1 page




74AC280 pdf
TEST CIRCUIT
74AC280
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL = R1 = 500Ω orequivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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