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PDF 74ABT841N Data sheet ( Hoja de datos )
| Número de pieza | 74ABT841N | |
| Descripción | 10-bit bus interface latch 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
10-bit bus interface latch (3-State)
Product specification
74ABT841
FEATURES
• High speed parallel latches
• Extra data width for wide address/data paths or buses carrying
parity
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Slim DIP 300 mil package
• Broadside pinout
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC = 5.5V
TYPICAL
4.1
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT841 N
–40°C to +85°C
74ABT841 D
–40°C to +85°C
74ABT841 DB
–40°C to +85°C
74ABT841 PW
NORTH AMERICA
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
TOP VIEW
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
13
OE
D0-D9
Output enable input
(active-Low)
Data inputs
Q0-Q9
LE
Data outputs
Latch enable input (active
falling edge)
12 GND Ground (0V)
24 VCC Positive supply voltage
SA00247
1995 Sep 06
1 853-1628 15703
1 page  
Philips Semiconductors
10-bit bus interface latch (3-State)
Product specification
74ABT841
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
LE pulse width
High or Low
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
3
3
1
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Min
2.5 1.0
1.5 0.0
2.5
1.5
1.5 0.2
1.0 –0.8
1.5
1.0
3.3 1.9
3.3
UNIT
ns
ns
ns
LE VM
VM
tw(H)
tPHL
Qn VM
VM
tPLH
VM
SA00248
Waveform 1. Propagation Delay, Latch Enable Input to Output,
and Enable Pulse Width
OE VM VM
tPZH
tPHZ
Qn VM VOH–0.3V
0V
SA00066
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Dn VM VM
tPLH
tPHL
Qn VM VM
SA00064
Waveform 2. Propagation Delay for Data to Outputs
Dn ÉÉÉÉÉÉÉÉÉVM ÉÉÉVM ÉÉÉÉÉÉÉÉÉÉÉÉVMÉÉÉÉÉÉVMÉÉÉÉÉÉ
ts(H)
th(H)
ts(L)
th(L)
LE VM
VM
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00249
Waveform 3. Data Setup and Hold Times
OE VM VM
tPZL
tPLZ
Qn VM VOL+0.3V
0V
SA00067
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1995 Sep 06
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ABT841N.PDF ] | |
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