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PDF 74ABT651D Data sheet ( Hoja de datos )
| Número de pieza | 74ABT651D | |
| Descripción | Octal transceiver/register/ inverting 3-State | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors
Octal transceiver/register, inverting (3-State)
Product specification
74ABT651
FEATURES
• Independent registers for A and B buses
• The 74ABT651 is the inverting version of the 74ABT652
• Multiplexed real-time and stored data
• 3-State outputs
• Live insertion/extraction permitted.
• Power-up 3-State
• Power-up reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT651 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT651 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT651.
The select pins determine whether data is stored or transferred
through the device in real time.
The output enable pins determine the direction of the data flow.
QUICK REFERENCE DATA
SYMBOL
tPLH
tPHL
CIN
CI/O
ICCZ
PARAMETER
Propagation delay
CPBA to An or CPAB to Bn
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.8
4.4
4
7
110
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT651 N
–40°C to +85°C
74ABT651 D
–40°C to +85°C
74ABT651 DB
–40°C to +85°C
74ABT651 PW
NORTH AMERICA
74ABT651 N
74ABT651 D
74ABT651 DB
74ABT651PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
CPAB 1
SAB 2
OEAB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CPBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
SA00094
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 23
2, 22
CPAB /
CPBA
SAB /
SBA
A to B clock input / B to A clock input
A to B select input / B to A select input
3, 21
OEAB /
OEBA
A to B Output Enable input /
B to A Output Enable input
(active–Low)
4, 5, 6, 7, 8,
9, 10, 11
A0 – A7 Data inputs/outputs (A side)
20, 19, 18,
17, 16, 15,
14, 13
B0 – B7 Data inputs/outputs (B side)
12 GND Ground (0V)
24 VCC Positive supply voltage
1995 Sep 06
1 853-1783 15703
1 page  
Philips Semiconductors
Octal transceiver/register, inverting (3-State)
Product specification
74ABT651
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK Input clamp voltage
VCC = 4.5V; IIK = –18mA
–0.9 –1.2
–1.2 V
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5 3.2
2.5
V
VOH High–level output voltage
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0 3.7
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0 2.30
2.0
V
VOL
VRST3
Low–level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
Power-up output low voltage VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.42 0.55
0.13 0.55
0.55 V
0.55 V
II
Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V
current
Data pins
VCC = 5.5V; VI = GND or 5.5V
±0.01 ±1.0
±5 ±100
±1.0
±100
µA
µA
IOFF Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
±5.0 ±100
±100 µA
IPU/IPD
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.5V; V OE = Don’t Care;
VI = GND or VCC
±5.0 ±50
±50 µA
IIH + IOZH 3–State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0 50
50 µA
IIL + IOZL 3–State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0 –50
–50 µA
ICEX
IO
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC
Output current1
VCC = 5.5V; VO = 2.5V
5.0 50
50 µA
–40 –65 –180 –40 –180 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
110 250
250 µA
ICCL
ICCZ
Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
20 30
110 250
30 mA
250 µA
∆ICC
Additional supply current per VCC = 5.5V; one input at 3.4V,
input pin2
other inputs at VCC or GND; VCC = 5.5V
0.3 1.5
1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Maximum clock frequency
Propagation delay
CPAB to Bn or CPBA to An
Propagation delay
An to Bn or Bn to An
Propagation delay
SAB to Bn or SBA to An
Output enable time
OEBA to An
Output disable time
OEBA to An
Output enable time
OEAB to Bn
Output disable time
OEAB to Bn
1
1
2
3
5
6
5
6
5
6
5
6
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ Max
125 300
2.2 3.8 5.1
1.7 4.4 5.1
1.5 3.2 5.1
1.5 3.7 4.6
1.5 3.8 5.1
1.5 4.4 4.9
1.3 3.7 4.6
2.5 4.7 6.8
1.5 4.0 4.5
1.5 3.2 3.8
1.8 3.4 6.1
2.9 4.5 6.5
1.5 3.8 4.5
1.5 3.1 4.4
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Min Max
125
2.2 5.6
1.7 5.6
1.5 6.2
1.5 5.4
1.5 6.5
1.5 5.9
1.3 5.8
2.5 8.5
1.5 5.0
1.5 4.1
1.8 6.5
2.9 7.4
1.5 5.5
1.5 5.1
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
1995 Sep 06
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ABT651D.PDF ] | |
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