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PDF 74ABT646CMTC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT646CMTC | |
| Descripción | Octal Transceivers and Registers with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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April 1992
Revised November 1999
74ABT646
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s A and B output sink capability of 64 mA, source capabil-
ity of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT646CSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide
74ABT646CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT646CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
OE
DIR
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
© 1999 Fairchild Semiconductor Corporation DS010978
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max Units
VCC
Conditions
CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.6 0.8 V 5.0 TA = 25°C (Note 6)
VOLV
Quiet Output Minimum Dynamic VOL
−1.2
−0.9
V 5.0 TA = 25°C (Note 6)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V 5.0 TA = 25° (Note 7)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.2 1.8
V 5.0 TA = 25°C (Note 8)
VILD Maximum LOW Level Dynamic Input Voltage
0.8 0.5 V 5.0 TA = 25°C (Note 8)
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Maximum Clock Frequency
Propagation Delay
Clock to Bus
Propagation Delay
Bus to Bus
Propagation Delay
SBA or SAB to An to Bn
Enable Time
OE to Anor Bn
Disable Time
OE to Anor Bn
Enable Time
DIR to An or B n
Disable Time
DIR to An or B n
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ
200
1.7 3.0
1.7 3.4
1.5 2.6
1.5 3.0
1.5 3.0
1.5 3.4
1.5 3.2
1.5 3.5
1.5 3.7
1.5 3.2
1.5 3.4
1.5 3.7
1.5 3.8
1.5 3.2
Max
5.6
5.6
4.8
4.8
5.9
5.9
6.3
6.3
6.0
6.0
6.3
6.3
6.0
6.0
AC Operating Requirements
TA = −55°C to +125°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
200
2.2 8.8
1.7 8.8
1.5 7.9
1.5 7.9
1.5 8.1
1.5 8.9
1.0 7.3
1.9 8.8
1.5 9.3
1.5 9.3
1.0 7.7
2.2 9.5
1.5 8.7
1.5 9.2
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
200
1.7 5.6
1.7 5.6
1.5 4.8
1.5 4.8
1.5 5.9
1.5 5.9
1.5 6.3
1.5 6.3
1.5 6.0
1.5 6.0
1.5 6.3
1.5 6.3
1.5 6.0
1.5 6.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
Setup Time, HIGH
or LOW Bus to Clock
Hold Time, HIGH
or LOW Bus to Clock
Pulse Width,
HIGH or LOW
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Max
1.5
TA = −55°C to +125°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
1.5 3.0 1.5
1.0 1.0 1.0 1.0
3.0 3.0 4.0 3.0
Units
ns
ns
ns
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