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What is 74ABT573CSC?

This electronic component, produced by the manufacturer "Fairchild Semiconductor", performs the same function as "Octal D-Type Latch with 3-STATE Outputs".


74ABT573CSC Datasheet PDF - Fairchild Semiconductor

Part Number 74ABT573CSC
Description Octal D-Type Latch with 3-STATE Outputs
Manufacturers Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 


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January 1993
Revised November 1999
74ABT573
Octal D-Type Latch with 3-STATE Outputs
General Description
The ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE)
inputs.
This device is functionally identical to the ABT373 but has
broadside pinouts.
Features
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to ABT373
s 3-STATE outputs for bus interfacing
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch-free bus loading during entire
power up and power down
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT573CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body
74ABT573CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT573CPC
N20A
20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-01, 0.300Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0D7
LE
OE
O0O7
Descriptions
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS011548
www.fairchildsemi.com

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74ABT573CSC equivalent
Extended AC Electrical Characteristics
(SOIC Package)
TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
(Note 9)
CL = 250 pF
8 Outputs Switching
Units
(Note 8)
(Note 10)
Min Max Min Max Min Max
tPLH Propagation Delay
tPHL
Dn to On
1.5 5.2 2.0 6.8 2.0 9.0
ns
1.5 5.2 2.0 6.8 2.0 9.0
tPLH Propagation Delay
tPHL
LE to On
1.5 5.5 2.0 7.5 2.0 9.5
ns
1.5 5.5 2.0 7.5 2.0 9.5
tPZH
tPZL
Output Enable Time
1.5 6.2 2.0 8.0 2.0 10.5
ns
1.5 6.2 2.0 8.0 2.0 10.5
tPHZ
tPLZ
Output Disable Time
1.0 5.5
1.0 5.5
(Note 11)
(Note 11)
ns
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 12)
(SOIC Package)
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
8 Outputs Switching
Units
(Note 12)
(Note 13)
Max Max
tOSHL (Note 14)
tOSLH (Note 14)
tPS (Note 15)
tOST (Note 14)
tPV (Note 16)
Pin to Pin Skew, HL Transitions
Pin to Pin Skew, LH Transitions
Duty Cycle, LHHL Skew
Pin to Pin Skew, LH/HL Transitions
Device to Device Skew LH/HL Transitions
1.0
1.0
1.4
1.5
2.0
1.5 ns
1.5 ns
3.5 ns
3.9 ns
4.0 ns
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.)
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST). This specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
Typ
CIN Input Capacitance
5
COUT (Note 17) Output Capacitance
9
Note 17: COUT is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
Units
pF
pF
VCC = 0V
VCC = 5.0V
Conditions
(TA = 25°C)
5 www.fairchildsemi.com


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Featured Datasheets

Part NumberDescriptionMFRS
74ABT573CSCThe function is Octal D-Type Latch with 3-STATE Outputs. Fairchild SemiconductorFairchild Semiconductor
74ABT573CSJThe function is Octal D-Type Latch with 3-STATE Outputs. Fairchild SemiconductorFairchild Semiconductor

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