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PDF 74ABT5074DB Data sheet ( Hoja de datos )
| Número de pieza | 74ABT5074DB | |
| Descripción | Synchronizing dual D-type flip-flop with metastable immune characteristics | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors Advanced BiCMOS Products
Synchronizing dual D-type flip-flop
with metastable immune characteristics
Product specification
74ABT5074
FEATURES
• Metastable immune characteristics
• Pin compatible with 74F74 and 74F5074
• Typical fMAX = 200MHz
• Output skew guaranteed less than 2.0ns
• High source current (IOH = 15mA) ideal for clock driver
applications
• Output capability: +20mA/–15mA
• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low-to-high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the
74ABT5074 are:
τ ≅ 94ps and To ≅ 1.3 × 107 sec
where τ represents a function of the rate at which a latch in a
metastable state resolves that condition and T0 represents a
function of the measurement of the propensity of a latch to enter a
metastable state.
PIN CONFIGURATION
RD0 1
D0 2
CP0 3
SD0 4
Q0 5
Q0 6
GND 7
14 VCC
13 RD1
12 D1
11 CP1
10 SD1
9 Q1
8 Q1
SA00001
PIN DESCRIPTION
PIN NUMBER SYMBOL
NAME AND FUNCTION
2, 12
D0, D1 Data inputs
3, 11
CP0, CP1 Clock inputs (active rising edge)
4, 10
SD0, SD1 Set inputs (active-Low)
1, 13
RD0, RD1 Reset inputs (active-Low)
5, 9
Q0, Q1
Data outputs (active-Low),
non-inverting
6, 8
Q0, Q1
Data outputs (active-Low),
inverting
7 GND Ground (0V)
14 VCC Positive supply voltage
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL CPn to Qn or Qn
CIN Input capacitance
ICC Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
2.8
2.4
3
2
UNIT
ns
pF
µA
ORDERING INFORMATION
PACKAGES
14-pin plastic DIP
14-pin plastic SOL
14-pin plastic shrink small outline SSOP Type II
14-pin plastic thin shrink small outline (TSSOP) Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDER CODE
74ABT5074N
74ABT5074D
74ABT5074DB
74ABT5074PW
DRAWING NUMBER
SOT27-1
SOT108-1
SOT337-1
SOT402-1
December 15, 1994
1
853-1775 14470
1 page  
Philips Semiconductors Advanced BiCMOS Products
Synchronizing dual D-type flip-flop
with metastable immune characteristics
Product specification
74ABT5074
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
MIN TYP MAX
Tamb = –40°C to +85°C
MIN MAX
VIK Input clamp voltage
VCC = 4.5V; IIK = –18mA
–0.9 –1.2
VOH
High-level output voltage
VCC = 4.5V; IOH = –15mA;
VI = VIL or VIH
2.5 2.9
2.5
VOL
Low-level output voltage
VCC = 4.5V; IOL = 20mA;
VI = VIL or VIH
0.35 0.5
II
Input leakage current
VCC = 5.5V; VI = GND or 5.5V
±0.01 ±1.0
IOFF Power-off leakage current VCC = 0.0V; VO or VI v 4.5V
IO Output current1
VCC = 5.5V; VO = 2.5V
±5.0 ±100
–50 –75 –180
–50
ICC Quiescent supply current VCC = 5.5V; VI = GND or VCC
2 50
∆ICC
Additional supply current VCC = 5.5V; one input at 3.4V,
per input pin2
other inputs at VCC or GND
0.25 500
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
–1.2
0.5
±1.0
±100
–180
50
500
UNIT
V
V
V
µA
µA
mA
µA
µA
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
MIN TYP MAX
Tamb = –40 to +85°C
VCC = +5.0V ±0.5V
MIN MAX
fmax Maximum clock frequency
1 180 250
150
tPLH Propagation delay
tPHL CPn to Qn or Qn
1
1.0 2.8 3.9
1.0 2.4 3.5
1.0
1.0
tPLH
tPHL
tsk(o)
Propagation delay
SDn, RDn to Qn or Qn
Output skew1, 2
CPn to Qn to Qn
2
1.0 3.5 4.6
1.0 3.1 4.2
1.0
1.0
4 1.5
NOTES:
1. | tPN actual - tPM actual | for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
4.5
3.7
5.5
4.7
2.0
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw (H)
tw (L)
tw (L)
trec
Setup time, High or Low
Dn to CPn
Hold time, High or Low
Dn to CPn
CPn pulse width,
high or low
SDn or RDn pulse width, low
Recovery time
SDn or RDn to CPn
1
1
1
2
3
LIMITS
Tamb = +25°C
VCC = +5.0V
MIN TYP
Tamb = –40 to +85°C
VCC = +5.0V ±0.5V
MIN
2.5 1.5
2.5 1.5
2.5
2.5
0 –1.4
0 –1.4
0
0
1.5 0.6
2.4 1.8
1.5
2.9
2.0 1.3
2.2
2.4 1.3
2.8
UNIT
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
December 15, 1994
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ABT5074DB.PDF ] | |
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