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PDF 74ABT2952CSC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT2952CSC | |
| Descripción | Octal Registered Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 1992
Revised November 1999
74ABT2952
Octal Registered Transceiver
General Description
The ABT2952 is an octal registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
Features
s Separate clock, clock enable and 3-STATE output
enable provided for each register
s A and B output sink capability of 64 mA source capability
of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT2952CSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT2952CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT2952CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
B0–B7
OEA
CPA
CEA
OEB
CPB
CEB
Description
A-Register Inputs/B-Register
3-STATE Outputs
B-Register Inputs/A-Register
3-STATE Outputs
Output Enable A-Register
A-Register Clock
A-Register Clock Enable
Output Enable B-Register
B-Register Clock
B-Register Clock Enable
© 1999 Fairchild Semiconductor Corporation DS010969
www.fairchildsemi.com
1 page  
Extended AC Electrical Characteristics
(SOIC Package)
TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
(Note 9)
CL = 250 pF
8 Outputs Switching
Units
(Note 8)
(Note 10)
Min Max Min Max Min Max
tPLH Propagation Delay
1.5 6.0 2.0 8.0 2.5 10.5
tPHL CPA or CPB to An or Bn
1.5 6.0 2.0 8.0 2.5 10.5
tPZH Output Enable Time
1.5 6.0 2.0 8.0 2.5 11.5
tPZL OEA or OEB to An or Bn
1.5 6.0 2.0 8.0 2.5 11.5
tPHZ Output Disable Time
tPZL OEA or OEB to An or Bn
1.5 6.0
1.5 6.0
(Note 11)
(Note 11)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
ns
ns
ns
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
8 Outputs Switching
Units
(Note 12)
(Note 13)
Max
Max
tOSHL
(Note 14)
Pin to Pin Skew
HL Transitions
1.0 1.5 ns
tOSLH
(Note 14)
Pin to Pin Skew
LH Transitions
1.0 2.0 ns
tPS
(Note 15)
Duty Cycle
LH–HL Skew
2.0 4.5 ns
tOST
(Note 14)
Pin to Pin Skew
LH/HL Transitions
2.1 4.5 ns
tPV
(Note 16)
Device to Device Skew
LH/HL Transitions
2.5 5.0 ns
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (tOST). This specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
Typ
CIN
CI/O (Note 17)
Input Capacitance
Output Capacitance
5
11
Note 17: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
Conditions
TA = 25°C
VCC = 0V (Non I/O Pins)
VCC = 5.0V (An, Bn)
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74ABT2952CSC.PDF ] | |
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