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PDF 74ABT244CPC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT244CPC | |
| Descripción | Octal Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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May 1992
Revised November 1999
74ABT244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT244 is an octal buffer and line driver with 3-STATE
outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver.
Features
s Non-inverting buffers
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
s Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Order Number Package Number
Package Description
74ABT244CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT244CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT244CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT244CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT244CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OE1, OE2
I0–I7
O0–O7
Output Enable Input
(Active LOW)
Inputs
Outputs
Truth Table
OE1 I0–3 O0–3 OE2 I4–7 O4–7
HXZHXZ
L HH L HH
LLLLLL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
© 1999 Fairchild Semiconductor Corporation DS010992
www.fairchildsemi.com
1 page  
AC Loading
*Includes jig and probe capacitance
AC Waveforms
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate
tW
tr
tf
3.0V
1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ABT244CPC.PDF ] | |
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