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Número de pieza | 74ABT16244 | |
Descripción | 16-Bit Buffer/Line Driver | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! April 1992
Revised May 2005
74ABT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual 3-
STATE control inputs can be shorted together for 8-bit or
16-bit operation.
Features
s Separate control logic for each nibble
s 16-bit version of the ABT244
s Outputs sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16244CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16244CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation DS010985
www.fairchildsemi.com
1 page Skew
TA 40qC to 85qC
TA 40qC to 85qC
VCC 4.5V–5.5V
VCC 4.5V–5.5V
Symbol
Parameter
CL 50 pF
16 Outputs Switching
CL 250 pF
16 Outputs Switching
Units
(Note 11)
(Note 12)
Max
Max
tOSHL
(Note 13)
Pin to Pin Skew
HL Transitions
1.0 1.5 ns
tOSLH
(Note 13)
Pin to Pin Skew
LH Transitions
1.0 1.5 ns
tPS
(Note 14)
Duty Cycle
LH–HL Skew
1.5 1.5 ns
tOST
(Note 13)
Pin to Pin Skew
LH/HL Transitions
1.7 2.0 ns
tPV
(Note 15)
Device to Device Skew
LH/HL Transitions
2.0 2.5 ns
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (tOST). The specification is guaranteed but not tested.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
Typ
CIN Input Capacitance
5.0
COUT (Note 16) Output Capacitance
9.0
Note 16: COUT is measured at frequency f 1 MHz; per MIL STD-883, Method 3012.
Units
pF
pF
VCC 5.0V
VCC 5.0V
Conditions
TA 25qC
5 www.fairchildsemi.com
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet 74ABT16244.PDF ] |
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