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PDF 74F160ASC Data sheet ( Hoja de datos )
| Número de pieza | 74F160ASC | |
| Descripción | Synchronous Presettable BCD Decade Counter | |
| Fabricantes | Fairchild Semiconductor | |
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April 1988
Revised July 1999
74F160A • 74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 74F160A and 74F162A are high-speed synchronous
decade counters operating in the BCD (8421) sequence.
They are synchronously presettable for applications in pro-
grammable dividers. There are two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
synchronous multistage counters. The F160A has an asyn-
chronous Master Reset input that overrides all other inputs
and forces the outputs LOW. The F162A has a Synchro-
nous Reset input that overrides counting and parallel load-
ing and allows all outputs to be simultaneously reset on the
rising edge of the clock. The F160A and F162A are high
speed versions of the F160 and F162.
Features
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count rate of 120 MHz
Ordering Code:
Order Number Package Number
Package Description
74F160ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F160ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F160APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F162ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F162APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F160A
74F162A
© 1999 Fairchild Semiconductor Corporation DS009485
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Maximum Count Frequency
Propagation Delay, Count
CP to Qn (PE Input HIGH)
Propagation Delay, Load
CP to Qn (PE Input LOW)
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
MR to Qn (74F160A)
Propagation Delay
MR to TC (74F160A)
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
90 120
3.5 5.5 7.5
3.5 7.5 10.0
4.0 6.0 8.5
4.0 6.0 8.5
5.0
10.0
14.0
5.0
10.0
14.0
2.5 4.5 7.5
2.5 4.5 7.5
5.5 9.0 12.0
TA = −55°C to +125°C
VCC = +5.0V
CL = 50 pF
Min Max
75
3.5 9.0
3.5 11.5
4.0 10.0
4.0 10.0
5.0 16.5
5.0 15.5
2.5 9.0
2.5 9.0
5.5 14.0
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
80
3.5 8.5
3.5 11.0
4.0 9.5
4.0 9.5
5.0 15.0
5.0 15.0
2.5 8.5
2.5 8.5
5.5 13.0
4.5 8.0 10.5 4.5 12.5 4.5 11.5
AC Operating Requirements
Symbol
Parameter
tS(H)
tS(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
tW(H)
tW(L)
tW(L)
tREC
Setup Time, HIGH or LOW
Pn to CP (74F160A)
Setup Time, HIGH or LOW
Pn to CP (74F162A)
Hold Time, HIGH or LOW
Pn to CP
Setup Time, HIGH or LOW
PE or SR to CP
Hold Time, HIGH or LOW
PE or SR to CP
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width (Load)
HIGH or LOW
Clock Pulse Width (Count)
HIGH or LOW
MR Pulse Width, LOW
(74F160A)
Recovery Time
MR to CP (74F160A)
TA = +25°C
VCC = +5.0V
Min Max
4.0
5.0
5.0
5.0
2.0
2.0
11.0
8.5
2.0
0
11.0
5.0
0
0
5.0
5.0
4.0
6.0
5.0
TA = −55°C to +125°C
VCC = +5.0V
Min Max
5.5
5.5
2.5
2.5
13.5
10.5
2.0
0
13.0
6.0
0
0
5.0
5.0
5.0
8.0
5.0
TA = 0°C to +70°C
VCC = +5.0V
Min Max
4.0
5.0
5.0
5.0
2.0
2.0
11.5
9.5
2.0
0
11.5
5.0
0
0
5.0
5.0
4.0
7.0
5.0
6.0 6.0 6.0
Units
MHz
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74F160ASC.PDF ] | |
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