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PDF 74ALVT16260 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVT16260 | |
| Descripción | 12-bit to 24-bit multiplexed D-type latches | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Rev. 03 — 20 March 2006
Product data sheet
1. General description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where
two separate data paths must be multiplexed onto, or demultiplexed from, a single data
path. Typical applications include multiplexing or demultiplexing of address and data
information in microprocessor or bus-interface applications. This device is also useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1 to A12, 1B1 to 1B12 and 2B1 to 2B12) are available for address
or data transfer. The output enable inputs (OE1B, OE2B, and OEA) control the bus
transceiver functions. OE1B and OE2B also allow bank control in the A to B direction.
Address or data information can be stored using the internal storage latches. The latch
enable inputs (LE1B, LE2B, LEA1B and LEA2B) are used to control data storage. When
the latch enable input is HIGH, the latch is transparent. When the latch enable input goes
LOW, the data present at the inputs is latched and remains latched until the latch enable
input is returned HIGH.
To ensure the high-impedance state during power-up or power-down, all output enable
inputs should be tied to VCC through a pull-up resistor. The minimum value of the resistor
is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a SSOP56 and a TSSOP56 package.
2. Features
I 5 V I/O compatible
I Bus hold inputs eliminate the need for external pull-up resistors
I Live insertion and extraction permitted
I Power-up 3-state
I Power-up reset
I Output capability: +64 mA and −32 mA
I Distributed VCC and GND pin configuration minimizes high-speed switching noise
I Latch-up protection:
N JESD78: exceeds 500 mA
I ESD protection:
N MIL STD 883C, method 3015: exceeds 2000 V
N Machine model: exceeds 200 V
芯天下--http://oneic.com/
1 page  
Philips Semiconductors
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
74ALVT16260_3
Product data sheet
Table 3.
Symbol
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
OE1B
LEA1B
1B4
GND
1B5
1B6
VCC
1B7
1B8
1B9
GND
1B10
1B11
1B12
2B12
2B11
2B10
GND
2B9
2B8
2B7
Pin description …continued
Pin Description
9 data input/output A2
10 data input/output A3
11 ground (0 V)
12 data input/output A4
13 data input/output A5
14 data input/output A6
15 data input/output A7
16 data input/output A8
17 data input/output A9
18 ground (0 V)
19 data input/output A10
20 data input/output A11
21 data input/output A12
22 supply voltage
23 1 data input/output B1
24 1 data input/output B2
25 ground (0 V)
26 1 data input/output B3
27 latch 2B to A enable input
28 select B1 or B2 input
29 output 1B enable input (active LOW)
30 latch A to 1B enable input
31 data input/output B4
32 ground (0 V)
33 1 data input/output B5
34 1 data input/output B6
35 supply voltage
36 1 data input/output B7
37 1 data input/output B8
38 1 data input/output B9
39 ground (0 V)
40 1 data input/output B10
41 1 data input/output B11
42 1 data input/output B12
43 2 data input/output B12
44 2 data input/output B11
45 2 data input/output B10
46 ground (0 V)
47 2 data input/output B9
48 2 data input/output B8
49 2 data input/output B7
Rev. 03 — 20 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 18
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Philips Semiconductors
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6;
Tamb = −40 °C to +85 °C
Symbol Parameter
Conditions
VCC = 3.3 V ± 0.3 V
tPLH LOW-to-HIGH propagation delay
An to xBn; xBn to An
see Figure 3
LExB to An; LEAxB to xBn
SEL(1Bn) to An
SEL(2Bn) to An
tPHL HIGH-to-LOW propagation delay
An to xBn; xBn to An
see Figure 3
LExB to An; LEAxB to xBn
SEL(1Bn) to An
SEL(2Bn) to An
tPZH output enable time to HIGH-state
see Figure 4
OEA to An; OE1B to 1Bn; OE2B to 2Bn
tPZL output enable time to LOW-state
see Figure 4
OEA to An; OE1B to 1Bn; OE2B to 2Bn
tPHZ output disable time from HIGH-state
see Figure 4
OEA to An; OE1B to 1Bn; OE2B to 2Bn
tPLZ output disable time from LOW-state
see Figure 4
OEA to An; OE1B to 1Bn; OE2B to 2Bn
tsu setup time
An to LEAxB; xBn to LExB
see Figure 5
th hold time
LEAxB to An; LExB to xBn
see Figure 5
tW pulse width
LExB HIGH; LEAxB HIGH
see Figure 5
Min Typ Max Unit
0.7 2.2 3.6 ns
1.0 2.4 4.1 ns
1.0 2.2 3.4 ns
0.9 2.3 3.8 ns
0.7 2.0 3.4 ns
1.1 2.3 3.9 ns
1.0 2.0 3.3 ns
1.6 2.1 3.4 ns
1.1 2.7 4.1 ns
1.1 2.1 3.2 ns
2.4 3.4 4.8 ns
2.0 3.0 4.0 ns
1 - - ns
1 - - ns
3.3 - - ns
74ALVT16260_3
Product data sheet
Rev. 03 — 20 March 2006
芯天下--http://oneic.com/
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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| PDF Descargar | [ Datasheet 74ALVT16260.PDF ] | |
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