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PDF 74ALVCH16374 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16374 | |
| Descripción | Low Voltage 16-Bit D-Type Flip-Flop with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2001
Revised February 2002
74ALVCH16374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
General Description
The ALVCH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVCH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16374 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74ALVCH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
4.2 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
7.8 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Descriptions
74ALVCH16374T
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500627
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fCLOCK
tW
tS
tH
fMAX
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
Clock Frequency
Pulse Width
Setup Time
Hold Time
Maximum Clock Frequency
Propagation Delay
Output Enable Time
Output Disable Time
TA = −40°C to +85°C, RL = 500Ω
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
150 150 150 100
3.3 3.3 3.3 4.0
1.9 2.2 2.1 2.5
0.5 0.5 0.6 1.0
150 150 150 100
1.0 4.2
4.9 1.0 5.3 1.5 7.8
1.0 4.8
5.9 1.0 6.2 1.5 9.2
1.0 4.3
4.7 1.0 5.3 1.5 6.8
Units
MHz
ns
ns
ns
MHz
ns
ns
ns
Capacitance
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Control
Data
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
Outputs Disabled f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 3
3.3 6
3.3 7
3.3 30
2.5 31
3.3 18
2.5 16
Units
pF
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16374.PDF ] | |
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