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PDF 74ALVCH16374 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16374 | |
| Descripción | 16-bit edge-triggered D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 5 — 9 July 2012
Product data sheet
1. General description
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)
input and an output enable (OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is
HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not
affect the state of the flip-flops.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines at 85 C
Current drive 24 mA at VCC = 3.0 V
1 page  
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1OE, 2OE
1, 24
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
2Q0 to 2Q7
13, 14, 16, 17, 19, 20, 22, 23
GND
4, 10, 15, 21, 28, 34, 39, 45
VCC
1D0 to 1D7
7, 18, 31, 42
47, 46, 44, 43, 41, 40, 38, 37
2D0 to 2D7
36, 35, 33, 32, 30, 29, 27, 26
1CP, 2CP
48, 25
6. Functional description
Description
output enable input (active LOW)
3-state flip-flop outputs
3-state flip-flop outputs
ground (0 V)
positive supply voltage
data inputs
data inputs
clock input
6.1 Function table
Table 3.
Inputs
nOE
L
L
H
H
Function table[1]
nCP
Dn
l
h
l
h
Internal
flip-flops
L
H
L
H
Outputs Q0 to Q7
L
H
Z
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
Operating mode
load and read register
load register and disable outputs
74ALVCH16374
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
Table 8. Measurement points
Supply voltage
Input
VCC
VI
2.3 V to 2.7 V and < 2.3 V VCC
2.7 V
2.7 V
3.0 V to 3.6 V
2.7 V
12. Test information
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
VM
0.5 VCC
1.5 V
1.5 V
Output
VM
0.5 VCC
1.5 V
1.5 V
VX
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VY
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
VI
G
VCC
DUT
VO
RT
VEXT
RL
CL RL
mna616
Fig 9.
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Load circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
2.3 V to 2.7 V and
< 2.3 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
2.7 V
2.7 V
tr, tf
2.0 ns
2.5 ns
2.5 ns
Load
CL
30 pF
50 pF
50 pF
RL
500
500
500
VEXT
tPLH, tPHL
open
tPLZ, tPZL
2 VCC
tPHZ, tPZH
GND
open
open
2 VCC
2 VCC
GND
GND
74ALVCH16374
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
11 of 17
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16374.PDF ] | |
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