74ALVC16835 Datasheet PDF - Fairchild Semiconductor
Part Number | 74ALVC16835 | |
Description | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs | |
Manufacturers | Fairchild Semiconductor | |
Logo | ||
There is a preview and 74ALVC16835 download ( pdf file ) link at the bottom of this page. Total 7 Pages |
Preview 1 page No Preview Available ! September 2001
Revised February 2002
74ALVC16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Ouputs (On) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVC16835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CLK to On)
4.5 ns max for 3.0V to 3.6V VCC
5.5 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC (OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Order Number
Package
Number
Package Description
74ALVC16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS500645
www.fairchildsemi.com
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IOUT - VOUT Characteristics
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Driver
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
5 www.fairchildsemi.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 74ALVC16835 electronic component. |
Information | Total 7 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ 74ALVC16835.PDF Datasheet ] |
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