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PDF 74ACTQ240 Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ240 | |
| Descripción | Quiet Series. Octal Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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July 1989
Revised November 1999
74ACQ240 • 74ACTQ240
Quiet Series Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The ACQ/ACTQ240 is an inverting octal buffer and line
driver designed to be employed as a memory address
driver, clock driver and bus oriented transmitter or receiver
which provides improved PC board density. The ACQ/
ACTQ utilizes Fairchild’s Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
s Outputs source/sink 24 mA
s Faster prop delays than the standard ACT240
Ordering Code:
Order Number Package Number
Package Description
74ACQ240SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body
74ACQ240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ240PC
74ACTQ240SC
74ACTQ240SJ
74ACTQ240QSC
N20A
M20B
M20D
MQA20
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE1, OE2
I0–I7
O0–O7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010234
www.fairchildsemi.com
1 page  
AC Electrical Characteristics for ACQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 13)
Min
Typ
Max
Min
Max
tPHL Propagation Delay
tPLH Data to Output
tPZL Output Enable Time
tPZH
tPHZ Output Disable Time
tPLZ
tOSHL
Output to Output Skew
tOSLH
Data to Output (Note 14)
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
3.3 2.0 7.0 10.0 2.0 10.5
5.0 1.5 5.0 6.5 1.5 7.0
3.3 2.5 8.0 12.0 2.5 12.5
5.0 1.5 5.5 8.0 1.5 8.5
3.3 1.0 8.5 13.5 1.0 14.0
5.0 1.0 6.0 9.0 1.0 9.5
3.3 1.0 1.5 1.5
5.0 0.5 1.0 1.0
ns
ns
ns
ns
Voltage Range 3.3 is 3.3 ± 0.3V.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Electrical Characteristics for ACTQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 15)
Min
Typ
Max
Min
Max
tPHL Propagation Delay
tPLH Data to Output
tPZL, tPZH
Output Enable Time
tPHZ, tPLZ
Output Disable Time
tOSHL
Output to Output Skew
tOSLH
Data to Output (Note 16)
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
5.0 1.5 5.5 7.0 1.5 7.5
5.0 1.5 6.5 8.5 1.5 9.0
5.0 1.0 7.0 9.5 1.0 10.0
5.0 0.5 1.0 1.0
ns
ns
ns
ns
Note 16: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = OPEN
70 pF VCC = 5.0V
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ240.PDF ] | |
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