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Número de pieza | 74ACTQ16374 | |
Descripción | 16-Bit D-Type Flip-Flop with 3-STATE Outputs | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! June 1991
Revised November 1999
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
The ACTQ16245 utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Buffered Positive edge-triggered clock
s Separate control logic for each byte
s 16-bit version of the ACTQ374
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16374SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin
Names
OEn
CPn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010935
www.fairchildsemi.com
1 page Extended AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF
TA = −40°C to +85°C
Symbol
Parameter
16 Outputs Switching
CL = 250 pF
Units
(Note 10)
(Note 11)
Min Typ Max Min Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 12)
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
Pin to Pin Skew
HL Data to Output
4.7 13.3 6.6 16.3
ns
4.6 11.4 6.4 15.5
3.5 10.4
(Note 13)
ns
3.8 10.9
3.4 8.5
(Note 14)
ns
3.1 8.1
1.3 ns
tOSLH
(Note 12)
Pin to Pin Skew
LH Data to Output
2.1 ns
tOST
(Note 12)
Pin to Pin Skew
LH/HL Data to Output
4.0 ns
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = 5.0V
30 pF VCC = 5.0V
5 www.fairchildsemi.com
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet 74ACTQ16374.PDF ] |
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