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PDF 74ACT573MTC Data sheet ( Hoja de datos )
| Número de pieza | 74ACT573MTC | |
| Descripción | Octal Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised October 1999
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
Features
s ICC and IOZ reduced by 50%
s Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to 74AC373 and 74ACT373
s 3-STATE outputs for bus interfacing
s Outputs source/sink 24 mA
s 74ACT573 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74AC573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74ACT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE 3-STATE Output Enable Input
O0–O7
3-STATE Latch Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009973
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACT
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5
2.0
2.0
5.5 1.5
2.0
2.0
4.5 1.5
0.8
0.8
5.5 1.5
0.8
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input
Leakage Current
5.5
±0.1
IOZ Maximum 3-STATE
Leakage Current
5.5
±0.25
ICCT
IOLD
IOHD
ICC
Maximum
ICC/Input
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5
4.0
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
±1.0
±2.5
1.5
75
−75
40.0
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 7)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 7)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
AC Electrical Characteristics for ACT
Symbol
Parameter
tPLH Propagation Delay
tPHL
Dn to On
tPLH Propagation Delay
LE to On
tPHL Propagation Delay
LE to On
tPZH Output Enable Time
tPZL Output Enable Time
tPHZ Output Disable Time
tPLZ Output Disable Time
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
2.5 6.0 10.5
3.0 6.0 10.5
2.5 5.5 9.5
2.0 5.5 10.0
1.5 5.5 9.5
2.5 6.5 11.0
1.5 5.0 8.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
2.0 12.0
2.5 12.0
2.0 10.5
1.5 11.0
1.5 10.5
1.5 12.5
1.0 9.5
Units
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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