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PDF 74ACT273B Data sheet ( Hoja de datos )
| Número de pieza | 74ACT273B | |
| Descripción | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74ACT273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 190 MHz ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT273 is a high-speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
PRELIMINARY DATA
B
(Plastic Package)
ORDER CODES :
74ACT273B
74ACT273M
74ACT273T
M
(Micro Package)
T
(TSSOP Package)
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs .
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1999
1/11
1 page  
74ACT273
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
tPLH Propagation Delay Time
tPHL CK to Q
tPLH Propagation Delay Time
tPHL CLR to Q
twL CLR pulse Width, LOW
tw CK pulse Width
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
tREM Recovery Time CLR to
CK
fMAX Maximum Clock
Frequency
(*) Voltage range is 5V ± 0.5V
T est Con ditio n
VCC
(V)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
1.5 6.5 8.5 1.5 9.0
Unit
ns
1.5 7.0 9.0 1.5 9.5
ns
1.5 4.0
1.0 4.0
1.0 3.5
4.0 ns
4.0 ns
3.5 ns
-0.5 1.5
1.5 ns
0.5 3.0
3.0 ns
125 190
110
MHz
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
5.0 fIN = 10 MHz
Capacitance (note 1)
32
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n(per circuit)
5/11
5 Page 
74ACT273
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
.
11/11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74ACT273B.PDF ] | |
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