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PDF 74ACT175 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT175 | |
| Descripción | QUAD D FLIP-FLOP WITH MASTER RESET | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74AC175
MC74ACT175
Quad D FlipĆFlop With
Master Reset
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for
general flip-flop requirements where clock and clear inputs are common. The
information on the D inputs is transferred to storage during the LOW-to-HIGH clock
transition. The device has a Master Reset to simultaneously clear all flip-flops, when
MR is low.
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and
Master Reset are common to all storage elements.
• Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs
QUAD D FLIP-FLOP
WITH MASTER RESET
N SUFFIX
CASE 648-08
PLASTIC
Pinout: 16-Lead Packages (Top View)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
12345678
MR Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMES
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Outputs
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
TRUTH TABLE
Inputs
Outputs
MR CP D Qn Qn
LXXLH
H HHL
H LLH
H L X Qn Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition of Clock
D0 D1 D2 D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
FACT DATA
5-1
1 page  
MC74AC175 MC74ACT175
AC CHARACTERISTICS
Symbol
Parameter
fmax
Maximum Clock
Frequency
tPLH
Propagation Delay
CP to Qn
tPHL
Propagation Delay
CP to Qn
tPHL
Propagation Delay
MR to Qn or Qn
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT
VCC*
(V)
TA = +25°C
CL = 50 pF
Min Typ Max
74ACT
TA = –40°C
to +85°C
CL = 50 pF
Min Max
5.0 175
145
Unit
MHz
5.0 2.0
10.0 1.5 11.0
ns
5.0 2.0
11.0 1.5 12.0
ns
5.0 2.0
9.5 1.5 10.5
ns
Fig.
No.
3-3
3-6
3-6
3-6
AC OPERATING REQUIREMENTS
Symbol
Parameter
ts (H) Set-up Time, HIGH or LOW
(L) Dn to CP
th
Hold Time, HIGH or LOW
Dn to CP
tw MR Pulse Width, LOW
tw
CP Pulse Width,
HIGH or LOW
trec
Recovery TIme
MR to CP
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT
74ACT
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
5.0
2.0
2.5
2.0
2.5
ns 3-9
5.0 1.0 1.0 ns 3-9
5.0 3.0 4.0 ns 3-6
5.0 3.0 3.5 ns 3-6
5.0 0 0 ns 3-6
CAPACITANCE
Symbol
Parameter
CIN
CPD
Input Capacitance
Power Dissipation Capacitance
Value
Typ
4.5
45.0
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
FACT DATA
5-5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ACT175.PDF ] | |
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