PDF 5962-9581501HXA Data sheet ( Hoja de datos )

Número de pieza	5962-9581501HXA
Descripción	Dual/ 12-Bit/ 40 MSPS MCM A/D Converter with Analog Input Signal Conditioning
Fabricantes	Analog Devices
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No Preview Available ! a Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioning AD10242 FEATURES Two Matched ADCs with Input Signal Conditioning Selectable Bipolar Input Voltage Range (؎0.5 V, ؎1.0 V, ؎2.0 V) Full MIL-STD-883B Compliant 80 dB Spurious-Free Dynamic Range Trimmed Channel-Channel Matching APPLICATIONS Radar Processing Communications Receivers FLIR Processing Secure Communications Any I/Q Signal Processing Application PRODUCT DESCRIPTION The AD10242 is a complete dual signal chain solution including onboard amplifiers, references, ADCs, and output buffering pro- viding unsurpassed total system performance. Each channel is laser trimmed for gain and offset matching and provides channel- to-channel crosstalk performance better than 80 dB. The AD10242 utilizes two each of the AD9631, OP279, and the AD9042 in a custom MCM to gain space, performance, and cost advantages over solutions previously available. The AD10242 operates with ± 5.0 V for the analog signal condi- tioning with a separate +5.0 V supply for the analog-to-digital conversion. Each channel is completely independent allowing operation with independent encode or analog inputs. The AD10242 also offers the user a choice of analog input signal ranges to minimize additional signal conditioning required for multiple functions within a single system. The heart of the AD10242 is the AD9042 which is designed specifically for appli- cations requiring wide dynamic range. The AD10242 is manufactured by Analog Devices on our MIL-PRF-38534 MCM line and is completely qualified. Units are packaged in a custom cofired ceramic 68-lead gull wing package and specified for operation from –55°C to +125°C. Contact the factory for additional custom options including those which allow the user to ac couple the ADC directly, by- passing the front end amplifier section. Also see the AD9042 data sheet for additional details on ADC performance. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 40 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals @ 80 dBc for –1 dBFS input signals. 3. Low power dissipation: <2 W off ± 5.0 V supplies. 4. User defined input amplitude. 5. Packaged in 68-lead ceramic leaded chip carrier. FUNCTIONAL BLOCK DIAGRAM AIN3 8 AIN2 7 AIN1 6 UNEG UCOM UPOS 56 55 57 AIN3 64 AIN2 63 AIN1 62 UPOS 12 UCOM 4 OP279 AD9631 OP279 AD9631 UNEG 3 (LSB) D0A 17 D1A 18 D2A 19 D3A 20 D4A 21 D5A 22 D6A 23 D7A 24 D8A 25 OP279 AD9042 VREF 12 9 OUTPUT BUFFERING TIMING 28 29 ENC ENC 31 D9A 32 33 D10A D11A (MSB) AD10242 OP279 AD9042 VREF TIMING 12 OUTPUT BUFFERING 5 7 52 ENC 51 ENC 49 D11B (MSB) 48 D10B 47 D9B 46 D8B 45 D7B 36 37 D0B D1B (LSB) 38 D2B 39 D3B 40 D4B 41 D5B 42 D6B REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 1 page Pin No. 1 2, 5, 9–11, 26–27 3 4 6 7 8 12 13 14 15–16 17–25, 31–33 28 29 30 34–35 36–42, 45–49 43–44, 53–54 58–61, 65, 68 50 51 52 55 56 57 62 63 64 66 67 Name SHIELD GNDA UNEGA UCOMA AINA1 AINA2 AINA3 UPOSA AVEE AVCC NC D0A–D11A ENCODEA ENCODEA DVCC NC D0B–D11B GNDB DVCC ENCODEB ENCODEB UCOMB UNEGB UPOSB AINB1 AINB2 AINB3 AVCC AVEE AD10242 PIN FUNCTION DESCRIPTIONS Function Internal Ground Shield between channels. A Channel Ground. A and B grounds should be connected as close to the device as possible. Unipolar Negative. Unipolar Common. Analog Input for A side ADC (nominally ± 0.5 V). Analog Input for A side ADC (nominally ± 1.0 V). Analog Input for A side ADC (nominally ± 2.0 V). Unipolar Positive. Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). Analog Positive Supply Voltage (nominally +5.0 V). No Connect. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital positive supply voltage (nominally +5.0 V). No Connect. Digital Outputs for ADC B. D0 (LSB). B Channel Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally +5.0 V). Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Unipolar Common. Unipolar Negative. Unipolar Positive. Analog Input for B side ADC (nominally ± 0.5 V). Analog Input for B side ADC (nominally ± 1.0 V). Analog Input for B side ADC (nominally ± 2.0 V). Analog Positive Supply Voltage (nominally +5.0 V). Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 GNDA 10 GNDA 11 UPOSA 12 AVEE 13 AVCC 14 NC 15 NC 16 (LSB) D0A 17 D1A 18 D2A 19 D3A 20 D4A 21 D5A 22 D6A 23 D7A 24 D8A 25 GNDA 26 PIN 1 AD10242 TOP VIEW (Not to Scale) 60 GNDB 59 GNDB 58 GNDB 57 UPOSB 56 UNEGB 55 UCOMB 54 GNDB 53 GNDB 52 ENCODEB 51 ENCODEB 50 DVCC 49 D11B (MSB) 48 D10B 47 D9B 46 D8B 45 D7B 44 GNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 REV. A NC = NO CONNECT –5– 5 Page AD10242 If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor, RX, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ, R2 = 8 kΩ). V1 = 5R2RX R1R2 + R1RX + R2RX to lower logic threshold. ENCODE SOURCE Vl 0.01µF RX ENCODE ENCODE +5V R1 AD10242 R2 Figure 21. Lower Threshold for Encode V1 = R2 5R2 + R1RX R1+ RX to raise logic threshold. AVCC ENCODE SOURCE RX Vl 0.01µF ENCODE ENCODE +5V R1 AD10242 R2 If no TTL source is available, a clean sine wave may be substi- tuted. In the case of the sine source, the matching network is shown below. Since the matching transformer specified is a 1:1 impedance ratio, R, the load resistor should be selected to match the source impedance. The input impedance of the AD9042 is negligible in most cases. SINE SOURCE T1-1T ENCODE R AD10242 ENCODE Figure 24. Sine Source—Differential Encode If a low jitter ECL clock is available, another option is to ac- couple a differential ECL signal to the encode input pins as shown below. The capacitors shown here should be chip capaci- tors but do not need to be of the low inductance variety. ECL GATE 510Ω 0.1µF 0.1µF 510Ω –VS ENCODE AD10242 ENCODE Figure 22. Raise Logic Threshold for Encode While the single ended encode will work well for many applica- tions, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is recom- mended that the encode signal be ac-coupled into the ENCODE and ENCODE pins. The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 Ω, to the pri- mary side of an RF transformer (these transformers are inexpen- sive and readily available; Part No. in figure is from Mini- Circuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs are self-biased, no additional components are required. 100Ω T1-1T TTL ENCODE AD10242 ENCODE Figure 25. Differential ECL for Encode As a final alternative, the ECL gate may be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal. AD96687 (1/2) 50Ω 510Ω 0.1µF 0.1µF 510Ω ENCODE AD10242 ENCODE –VS Figure 26. ECL Comparator for Encode Care should be taken not to overdrive the encode input pin when ac coupled. Although the input circuitry is electrically pro- tected from over or under voltage conditions, improper circuit operations may result from overdriving the encode input pin. Figure 23. TTL Source—Differential Encode REV. A –11– 11 Page

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