M27W201-80F6TR Datasheet PDF - STMicroelectronics
Part Number | M27W201-80F6TR | |
Description | 2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM | |
Manufacturers | STMicroelectronics | |
Logo | ||
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2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM
s 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
s ACCESS TIME:
– 70ns at VCC = 3.0V to 3.6V
– 80ns at VCC = 2.7V to 3.6V
s PIN COMPATIBLE with M27C2001
s LOW POWER CONSUMPTION:
– 15µA max Standby Current
– 15mA max Active Current at 5MHz
s PROGRAMMING TIME 100µs/byte
s HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
DESCRIPTION
The M27W201 is a low voltage 2 Mbit EPROM of-
fered in the two range UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organised as 262,144 by 8
bits.
The M27W201 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C tem-
perature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery re-
charges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27W201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
32
1
FDIP32W (F)
32
1
PDIP32 (B)
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC VPP
18
A0-A17
8
Q0-Q7
P M27W201
E
G
VSS
AI01359
April 2000
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M27W201
Table 7. Read Mode DC Characteristics (1)
(TA = –40 to 85 °C; VCC = 2.7V to 3.6V; VPP = VCC)
Symbol
Parameter
Test Conditio n
Min
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
ICC1
ICC2
IPP
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
VCC ≤ 3.6V
E = VIH
E > VCC – 0.2V
VCC ≤ 3.6V
VPP = VCC
VIL Input Low Voltage
–0.6
VIH (2) Input High Voltage
0.7 VCC
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage TTL
IOH = –400µA
2.4
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Max
±10
±10
15
1
15
10
0.2 VCC
VCC + 0.5
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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