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Número de pieza | 100397QC | |
Descripción | Quad Differential ECL/TTL Translating Transceiver with Latch | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 100397QC (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
No Preview Available ! January 1992
Revised August 2000
100397
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100397 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25Ω ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100397 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100397 accepts F100K ECL
logic levels. An ECL LOW on DIR sets up the ECL pins as
inputs and TTL pins as outputs. An ECL HIGH on DIR sets
up the TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitterfol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100397 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 KΩ pull-down resistors.
Features
s Differential ECL input/output structure
s 64 mA FAST TTL outputs
s 25Ω differential ECL outputs with cut-off
s Bi-directional translation
s 2000V ESD protection
s Latched outputs
s 3-STATE outputs
s Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Order Number Package Number
Package Description
100397PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100397QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100397QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010971
www.fairchildsemi.com
1 page Commercial Version (Continued)
ECL-to-TTL DC Electrical Characteristics (Note 9)
VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VOH
VOL
VIH
VIL
VDIFF
VCM
IIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Voltage Differential
Common Mode Voltage
Input HIGH Current
E0–E3, E0–E3
OE, LE, DIR
2.7
2.4
−1165
3.1
2.9
0.3
0.5
−870
V IOH = −3 mA, VTTL = 4.75V
V IOH = −3 mA, VTTL = 4.50V
V IOL = 24 mA, VTTL = 4.50V
mV Guaranteed HIGH Signal for All Inputs
−1830
−1475
mV Guaranteed LOW Signal for All Inputs
150 mV Required for Full Output Swing
GNDECL − 2.0
GNDECL − 0.5
V
240 µA VIN = VIH(Max)
35
ICEX
Output HIGH
Leakage Current
50 µA VOUT = VTTL
IZZ
IIL
IOZHT
Bus Drainage Test
Input LOW Current
3-STATE Current
Output High
0.50
500 µA VOUT = 5.25V
VTTL = 0.0V
µA VIN = VIL(Min)
70 µA VOUT = +2.7V
IOZLT
3-STATE Current
Output Low
−650
µA VOUT = +0.5V
IOS Output Short-Circuit
Current
−100
−225
mA VOUT = 0.0V, VTTL = +5.5V
ITTL VTTL Supply Current
39 mA TTL Outputs LOW
27 mA TTL Outputs HIGH
39 mA TTL Outputs in 3-STATE
Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
DIP and PCC TTL-to-ECL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V
Symbol
Parameter
TC = 0°C
Min Max
fMAX
Maximum Clock Frequency
180
tPLH
Tn to En, En
tPHL (Transparent)
0.9 2.1
tPLH
tPHL
LE to En, En
1.2 2.3
tPZH
OE to En, En
(Cutoff to HIGH)
2.5 4.5
TC = 25°C
Min Max
180
0.8 2.2
1.3 2.4
2.5 4.5
TC = 85°C
Min Max
180
0.7 2.5
1.4 2.5
2.5 4.6
tPHZ
OE to En, En
(HIGH to Cutoff)
2.1 3.8 2.3 4.0 2.5 4.5
tPHZ
DIR to En, En
(HIGH to Cutoff)
tS Tn to LE
tH Tn to LE
tTLH Transition Time
tTHL 20% to 80%, 80% to 20%
2.0 3.5 2.1 3.7 2.3 4.2
0.8 0.8 0.8
0.6 0.6 0.6
0.8 2.8 0.8 2.8 0.8 2.8
Units
MHz
Conditions
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
5 www.fairchildsemi.com
5 Page Test Circuitry (ECL-to-TTL) (Continued)
Note:
DIR is LOW, LE is HIGH
FIGURE 5. ECL-to-TTL Transition, OE to TTL Output,
Enable and Disable Times
Note:
OE is HIGH, LE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output,
Disable Time
Applications
FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100397 ECL–TTL Latched Translator
11 www.fairchildsemi.com
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet 100397QC.PDF ] |
Número de pieza | Descripción | Fabricantes |
100397QC | Quad Differential ECL/TTL Translating Transceiver with Latch | Fairchild Semiconductor |
100397QI | Quad Differential ECL/TTL Translating Transceiver with Latch | Fairchild Semiconductor |
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