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Número de pieza | 100370F | |
Descripción | Low Power Universal Demultiplexer/Decoder | |
Fabricantes | National Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 100370F (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! August 1998
100370
Low Power Universal Demultiplexer/Decoder
General Description
The 100370 universal demultiplexer/decoder functions as ei-
ther a dual 1-of-4 decoder or as a single 1-of-8 decoder, de-
pending on the signal applied to the Mode Control (M) input.
In the dual mode, each half has a pair of active-LOW Enable
(E) inputs. Pin assignments for the E inputs are such that in
the 1-of-8 mode they can easily be tied together in pairs to
provide two active-LOW enables (E1a to E1b, E2a to E2b).
Signals applied to auxiliary inputs Ha, Hb and Hc determine
whether the outputs are active HIGH or active LOW. In the
dual 1-of-4 mode the Address inputs are A0a, A1a and A0b,
A1b with A2a unused (i.e., left open, tied to VEE or with LOW
signal applied). In the 1-of-8 mode, the Address inputs are
A0a, A1a, A2a with A0b and A1b LOW or open. All inputs have
50 kΩ pulldown resistors.
Features
n 35% power reduction of the 100170
n 2000V ESD protection
n Pin/function compatible with 100170
n Voltage compensated operating range = −4.2V to −5.7V
Logic Symbols
Single 1-of 8 Application
Dual 1-of-4 Application
DS100311-1
Pin Names
Ana, Anb
Ena, Enb
M
Ha
Hb
Hc
Z0– Z7
Zna, Znb
Description
Address Inputs
Enable Inputs
Mode Control Input
Z0–Z3 (Z0a–Z3a)
Polarity Select Input
Z4–Z7 (Z0b–Z3b)
Polarity Select Input
Common Polarity
Select Input
Single 1-of-8
Data Outputs
Dual 1-of-4
Data Outputs
© 1998 National Semiconductor Corporation DS100311
DS100311-4
www.national.com
1 page AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
Min Max
TC = +25˚C
Min Max
TC = +125˚C Units
Min Max
Conditions
Notes
tPLH Propagation Delay
0.3 2.40 0.4 2.20 0.40 2.70 ns
tPHL
Ena, Enb to Output
tPLH Propagation Delay
0.30 2.60 0.40 2.40 0.40 2.90 ns
tPHL
Ana, Anb to Output
(Notes 9, 10,
tPLH Propagation Delay
0.30 2.60 0.40 2.40 0.40 2.40 ns Figures 1, 2
11)
tPHL
Ha, Hb, Hc to Output
tPLH Propagation Delay
0.40 3.10 0.60 2.80 0.70 3.70 ns
tPHL M to Output
tTLH Transition Time
0.30 1.60 0.30 1.60 0.30 1.60 ns
(Note 12)
tTHL 20% to 80%, 80% to 20%
Note 9: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 10: Screen tested 100% on each device at +25˚C, temperature only, Subgroup A9.
Note 11: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 and A11.
Note 12: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
Test Circuit
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
Pin numbers shown are for flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
DS100311-7
5 www.national.com
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet 100370F.PDF ] |
Número de pieza | Descripción | Fabricantes |
100370 | Low Power Universal Demultiplexer/Decoder | National Semiconductor |
100370 | Low Power Universal Demultiplexer/Decoder | Fairchild Semiconductor |
100370D | Low Power Universal Demultiplexer/Decoder | National Semiconductor |
100370F | Low Power Universal Demultiplexer/Decoder | National Semiconductor |
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