100354QC Datasheet PDF - Fairchild Semiconductor
| Part Number | 100354QC | |
| Description | Low Power 8-Bit Register with Cut-Off Drivers | |
| Manufacturers | Fairchild Semiconductor | |
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October 1989
Revised August 2000
100354
Low Power 8-Bit Register with Cut-Off Drivers
General Description
The 100354 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (Dn), true outputs (Qn),
a clock input (CP), an output enable pin (OEN), and a com-
mon clock enable pin (CEN). Data enters the master when
CP is LOW and transfers to the slave when CP goes HIGH.
When the CEN input goes HIGH it overrides all other
inputs, disables the clock, and the Q outputs maintain the
last state.
A Q output follows its D input when the OEN pin is LOW. A
HIGH on OEN holds the outputs in a cut-off state. The cut-
off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is −2.0V, presenting a
high impedance to the data bus. This high impedance
reduces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100354 outputs are designed to drive a doubly termi-
nated 50Ω transmission line (25Ω load impedance). All
inputs have 50 kΩ pull-down resistors.
Features
s Cut-off drivers
s Drives 25Ω load
s Low power operation
s 2000V ESD protection
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100354PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100354QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100354QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
Description
D0–D7
CEN
Data Inputs
Clock Enable Input
CP Clock Input (Active Rising Edge)
OEN
Output Enable Input
Q0–Q7
Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010610
28-Pin PLCC
www.fairchildsemi.com
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Industrial Version
PLCC DC Electrical Characteristics (Note 7)
VEE=−4.2V to −5.7V, VCC= VCCA= GND, TC=−40°C to +85°C
Symbol
Parameter
TC = −40°C
Min Max
TC = 0° to +85°C
Min Max
Units
Conditions
VOH
VOL
VOHC
VOLC
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
−1085
−1830
−1095
−870
−1575
−1565
−1025
−1830
−1035
−870
−1620
−1610
mV VIN =VIH (Max)
or VIL (Min)
mV VIN = VIH (Min)
or VIL (Max)
Loading with
50Ω to −2.0V
Loading with
50Ω to −2.0V
VOLZ
VIH
Cutoff LOW Voltage
Input HIGH Voltage
−1900
−1950
−1170
−870
−1165
−870
mV VIN = VIH (Min)
OEN = HIGH
or VIL (Max)
mV Guaranteed HIGH Signal
for All Inputs
VIL Input LOW Voltage
−1830 −1480 −1830 −1475
mV Guaranteed LOW Signal
for All Inputs
IIL Input LOW Current
0.50
0.50
µA VIN = VIL (Min)
IIH Input HIGH Current
240 240 µA VIN = VIH (Max)
IEE Power Supply Current
Inputs Open
−202
−105
−202
−105
mA VEE = −4.2V to −4.8V
−209
−105
−209
−105
VEE = −4.2V to −5.7V
Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −40°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
fMAX
tPLH
tPHL
tPZH
tPHZ
tTLH
tTHL
tS
Toggle Frequency
Propagation Delay
CP to Output
Propagation Delay
OEN to Output
Transition Time
20% to 80%, 80% to 20%
Setup Time
Dn
CEN (Disable Time)
250
1.40
1.50
1.00
0.45
2.80
4.10
2.50
1.90
250
1.40
1.60
1.00
0.45
2.80
4.00
2.50
1.90
250
1.50
1.60
1.00
0.45
2.90
4.00
2.50
1.90
MHz
ns
ns
ns
1.00
0.30
1.00
0.30
1.00
0.30
ns
CEN (Release Time)
1.00
1.00
1.00
tH Hold Time
0.00
0.00
0.00
Dn
tPW(H)
Pulse Width High
2.00
2.00
2.00
CP
ns
ns
Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Conditions
Figures 1, 4
Figures 1, 4
(Note 8)
Figures 3, 5
(Note 8)
Figures 1, 4
Figures 2, 5
Figures 1, 6
Figures 1, 4
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 100354QC electronic component. |
| Information | Total 9 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 100354QC.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| 100354QC | The function is Low Power 8-Bit Register with Cut-Off Drivers. Fairchild Semiconductor | |
| 100354QI | The function is Low Power 8-Bit Register with Cut-Off Drivers. Fairchild Semiconductor | |
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