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Número de pieza | 100351PC | |
Descripción | Low Power Hex D-Type Flip-Flop | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 100351PC (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! July 1988
Revised August 2000
100351
Low Power Hex D-Type Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CPa and CPb) and common Master
Reset (MR) input. Data enters a master when both CPa
and CPb are LOW and transfers to the slave when CPa and
CPb (or both) go HIGH. The MR input overrides all other
inputs and makes the Q outputs LOW. All inputs have
50 kΩ pull-down resistors.
Features
s 40% power reduction of the 100151
s 2000V ESD protection
s Pin/function compatible with 100151
s Voltage compensated operating range:
−4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100351SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100351PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100351QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100351QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
D0–D5
CPa, CPb
MR
Q0–Q5
Q0–Q5
Description
Data Inputs
Common Clock Inputs
Asynchronous Master Reset Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS009885
28-Pin PLCC
www.fairchildsemi.com
1 page Industrial Version
PLCC DC Electrical Characteristics
VEE=−4.2V to −5.7V, VCC=VCCA= GND, TC= 0°C to +85°C (Note 5)
Symbol
Parameter
TC = −40°C
Min Max
TC = 0° to +85°C
Min Max
Units
Conditions
VOH
VOL
VOHC
VOLC
VIH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
−1085
−1830
−1095
−1170
−870
−1575
−1565
−870
−1025
−1830
−1035
−1165
−870
−1620
−1610
−870
mV VIN =VIH (Max)
or VIL (Min)
Loading with
50Ω to −2.0V
mV VIN = VIH (Min)
or VIL (Max)
Loading with
50Ω to −2.0V
mV Guaranteed HIGH Signal
for All Inputs
VIL Input LOW Voltage
−1830 −1480 −1830 −1475
mV Guaranteed LOW Signal
for All Inputs
IIL Input LOW Current
IIH Input HIGH Current
0.50
0.50
MR 350
350
µA VIN = VIL (Min)
D0–D5
240
240 µA VIN = VIH (Max)
CPa, CPb
350
350
IEE Power Supply Current
−129 −62 −129 −62
mA Inputs OPEN
Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tS
tH
tPW(H)
Toggle Frequency
Propagation Delay
CPa, CPb to Output
Propagation Delay
MR to Output
Transition Time
20% to 80%, 80% to 20%
Setup Time
D0–D5
MR (Release Time)
Hold Time
D0–D5
Pulse Width HIGH
CPa, CPb, MR
TC = −40°C
Min Max
375
0.80
1.80
1.10
2.10
0.45
1.70
0.60
2.20
0.60
2.00
TC = +25°C
Min Max
375
0.80
1.80
1.10
2.10
0.45
1.60
0.30
1.50
0.90
2.00
TC = +85°C
Min Max
375
0.90
1.90
1.20
2.20
0.45
1.70
Units
Conditions
MHz Figures 2, 3
ns Figures 1, 3
ns Figures 1, 4
ns Figures 1, 3
0.30
1.50
0.90
2.00
ns Figure 5
Figure 4
ns Figure 5
ns Figures 3, 4
5 www.fairchildsemi.com
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet 100351PC.PDF ] |
Número de pieza | Descripción | Fabricantes |
100351PC | Low Power Hex D-Type Flip-Flop | Fairchild Semiconductor |
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