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What is DAC0830LCM?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "8-Bit P Compatible/ Double-Buffered D to A Converters".


DAC0830LCM Datasheet PDF - National Semiconductor

Part Number DAC0830LCM
Description 8-Bit P Compatible/ Double-Buffered D to A Converters
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
n Works with ±10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 µs
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation DS005608
DS005608-1
www.national.com

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DAC0830LCM equivalent
Electrical Characteristics (Continued)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-
age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF=±10 VDC and VREF=±1 VDC.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees that
after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a straight
line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x10−9x20x103)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kresistor.
Switching Waveform
DS005608-2
5 www.national.com


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On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for DAC0830LCM electronic component.


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