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What is 16C2850?

This electronic component, produced by the manufacturer "Exar Corporation", performs the same function as "DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX CONTROL".


16C2850 Datasheet PDF - Exar Corporation

Part Number 16C2850
Description DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX CONTROL
Manufacturers Exar Corporation 
Logo Exar Corporation Logo 


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Preliminary
Information
XR16C2850
DUAL UART WITH 128-byte FIFO’s AND
RS-485 HALF DUPLEX CONTROL
DESCRIPTION
The XR16C2850 (2850) is a dual universal asynchronous receiver and transmitter (UART). The 2850 provides
enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface,
and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational
status. System interrupts and modem control features may be tailored by external software to meet specific user
requirements. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate
generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can
be configured for either crystal or external clock input. The 2850 is available in a 40-pin PDIP, 44-pin PLCC, and
48-pin TQFP packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring).
Otherwise the three package versions are the same. The 2850 is functionally compatible with the ST16C2550.
The 2850 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
FEATURES
Pin and functionally compatible to ST16C2550,
software compatible with INS8250, NS16C550
1.5 Mbps transmit/receive operation (24 MHz
Max.).
128 byte transmit FIFO to reduce bandwidth re-
quirement of the external CPU.
128 byte receive FIFO with error flags to reduce
bandwidth requirement of the external CPU.
Independent transmit and receive UART control.
RS-485 half duplex control.
Programmable transmit/receive FIFO trigger lev-
els.
Hardware / software flow control.
Selectable RTS flow control hysterisis.
Modem control signals (-CTS, -RTS, -DSR, -DTR,
-RI, -CD, and software controllable line break).
Programmable character lengths (5, 6, 7, 8) with
even, odd, or no parity.
Infrared receive and transmit encoder/decoder.
Device identification.
Crystal or external clock input.
460.8 Kbps transmit/receive operation with 7.3728
MHz crystal or external clock source.
D5 7
D6 8
D7 9
RXB 10
RXA 11
-TXRDYB 12
TXA 13
TXB 14
-OPB 15
-CSA 16
-CSB 17
PLCC Package
XR16C2850CJ
39 RESET
38 -DTRB
37 -DTRA
36 -RTSA
35 -OPA
34 -RXRDYA
33 INTA
32 INTB
31 A0
30 A1
29 A2
ORDERING INFORMATION
Part number
XR16C2850CP
XR16C2850CJ
XR16C2850CM
Pins Package
40 PDIP
44 PLCC
48 TQFP
Operating temperature
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
Part number
XR16C2850IP
XR16C2850IJ
XR16C2850IM
Pins Package
40 PDIP
44 PLCC
48 TQFP
Operating temperature
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
Rev. 1.00P
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017

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16C2850 equivalent
XR16C2850
SYMBOL DESCRIPTION
Symbol
-OP2 A-B
Pin Signal
40 44 48 type
Pin Description
31,13 35,15 32,9 O Output -2 (User Defined) - This function is associated with
individual channels, A through B. The state at these pin(s)
are defined by the user and through the software setting of
MCR register bit-3. INT A-B are set to the active mode and
OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are
set to the three state mode and OP2 to a logic 1 when MCR-
3 is set to a logic 0. See bit-3, Modem Control Register
(MCR bit-3).
RESET
35 39 36
I Reset (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time (see XR16C2850 External Reset Conditions for initial-
ization details).
-RXRDY A-B
- 34,23 31,18 O Receive Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only. This
function provides the RX FIFO/RHR status for individual
receive channels (A-B). RXRDY is primarily intended for
monitoring DMA mode 1 transfers for the receive data
FIFO’s. A logic 0 indicates there is receive data to read/
unload, i.e., receive ready status with one or more RX
characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
-TXRDY A-B
- 1,12 43,6 O Transmit Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only.
These outputs provide the TX FIFO/THR status for indi-
vidual transmit channels (A-B). TXRDY is primarily in-
tended for monitoring DMA mode 1 transfers for the trans-
mit data FIFO’s. An individual channel’s -TXRDY A-B buffer
ready status is indicated by logic 0, i.e., at least one location
is empty and available in the FIFO or THR. This pin goes to
a logic 1 when there are no more empty locations in the
FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
VCC
40 44 42 Pwr Power supply input.
Rev. 1.00P
5


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Featured Datasheets

Part NumberDescriptionMFRS
16C2850The function is DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX CONTROL. Exar CorporationExar Corporation

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